SU1529454A1 - Analog-digital converter - Google Patents

Abstract

The invention relates to analog-to-digital converters and can be used in communication systems, computing, automatic control and monitoring systems. Expansion of the field of use due to the possibility of automated control of the output code is achieved by introducing into the converter, containing two comparators 1 and 2, element 2И-НЕ 4, two elements И 9 and 10, reversible counter 12, converter code-voltage 14, RS-flip-flop 8, two elements EXCLUSIVE OR 5 and 6, the third comparator 3, the source 11 of the reference voltage and the switch 13. Control of the conversion process is achieved due to the fact that when the voltage at the output of the code-voltage converter 14 is equal to the voltage on the input bus not U _in , then comparators 1 and 2 change their state to the opposite and element 2И-НЕ 4 generates a stop signal at the S input of the RS flip-flop 8, which disables the counting mode in the reversing counter 12, and turns on the recording mode, and the signal The trigger is applied to the R input of trigger 8. 1 Il.

Description

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Sign rank

The invention relates to analog-to-digital converters and can be used in communication systems, computer technology, as well as in automatic process control systems in scientific automation systems.

The purpose of the invention is to expand the scope of use due to the possibility of fixing a reliable output code.

The drawing shows the functional diagram of the analog-to-digital Converter.

The Converter contains the first 1 and second 2 Comparators, the third Comparator 3, element 2I-NOT 4, elements 5 and 6 EXCLUSIVE OR, generator

7 clock pulses, RS flip-flop 8, elements 9 and 10, reference voltage source 11, reversible counter 12, reference voltage switch 13, code converter 14 - voltage.

The converter works as follows.

The conversion cycle begins with the arrival of the Start signal at the R input of the RS flip-flop 8, which changes its state and enables the counting mode in a reversible counter 12o

The pulses from the generator 7 are fed through one of the elements AND (9 or 10) to the input. Addition or Subtraction of the reversible counter 12 "

Elements 9 and 10 are controlled by elements 5 and 6 EXCLUSIVE OR Comparators 1, 2 and 3.

Comparators 1 and 2 are united by their opposite inputs and are in opposite states, which depend on the voltage ratio on the input bus II. and at the output of the converter 14, the code is a voltage that is determined by the code of the reversible counter 12,

To convert a voltage of another polarity, it is necessary to change the sign of the reference voltage supplied from the source 11 of the reference voltage through the switch 13 of the reference voltage, which controls the sign of the reference voltage depending on the state of the comparator 3 comparing the voltage on the input bus to zero voltage common bus, it is also necessary to change the direction of counting in the reversible counter 12, which is carried out by the schemes EXCLUSIVE

OR 5 and 6, which function as an inverter or repeater.

The counting in the reversible counter 12 will continue until the voltage at the output of the converter 14 is equal to the voltage on the input bus Ugy. Then comparators 1 and 2 change their state to the opposite, and element 2I-HE 4 generates a Stop signal for an 8-time RS-flip-flop 8, which disables the counting mode in the reversing counter 12 and turns on the recording mode,

The reversing counter 12 records the code that was output.

before entering the recording mode, In this

state, the reversible counter 12 is located before the next start signal arrives

The inputs of the reversible counter 12 are output length, the code of its

the output will be reliable during the operation of the reversible counter 12 in the recording mode. If necessary, the code validity signal can be removed from the RS flip-flop 8

Claims (1)

Invention Formula An analog-to-digital converter containing two comparators, the outputs of which are connected to the inputs of the NAND element, two elements AND, the first inputs of which are connected to the output of the clock generator, and the outputs are connected to the corresponding inputs of the control of the reversible counter, the outputs of which are output bus and connected to the corresponding inputs of the converter code - voltage, the output of which is connected to the first inputs of the comparators, the source of the reference voltage, characterized in that, in order to expand the area application due to the possibility of fixing a reliable output code, an RS-trigger, a third comparator, two EXCLUSIVE OR elements, and a switch, the output of which is connected to the input of the reference voltage, are entered, the first input is connected to the output of the reference voltage source, and the input is a bus the sign, combined with the first inputs of the first and second elements EXCLUSIVE OR, and connected to the output of the third comparator, the first input of which is a bus of zero potential, and the second input combined with the second inputs of the first and second comparators and is an input bus ,. the output of the NAND element is connected to the S-BXO- ryh connected to the outputs by an appropriate RS-flip-flop, the R-input of which of the comparators. The bus is started and the output is connected to the control mode input of the reversible counter, the inputs of which are connected to the corresponding outputs of the reversible counter, the second inputs of the elements AND are connected to the outputs of the corresponding elements EXCLUSIVE OR, the BOTpbie inputs are