SU900444A1 - Method and device for converting alternating current to frequency - Google Patents

Description

The invention relates to measurement technology and is intended for use in automation systems, in particular, for converting signals from sensors. A known method of converting current into frequency, concluding in integrating the input signal to the horn level and balancing the input signal, is a sequence of standard current pulses, formed at the moments when the threshold analogue I1 is reached. Its disadvantage is the impossibility of converting the signal of both polarities. A known method of converting an alternating current into a frequency is to integrate the input signal to one of two threshold levels, corresponding to the polarity of the input signal, and to generate reference current pulses of balancing polarity in the moment. You reach the threshold level and balance the input signal with a sequence of reference current pulses 2. A converter of alternating current into a frequency containing the first and second comparators, the first inputs of which are connected to the integrating capacitor, and the second inputs to the first and second sources gTaJtOHHO. voltage, and the pulse generator of the reference duration, the first and second outputs of which are connected / respectively, to the first and second inputs of the reverse pulse generator current of 2,. The shortage of 5 m of the known method and device is the presence of additional errors due to the instability of the threshold levels of the integrating capacitor in the periods and the output frequency, in which the polarity of the input signal is changed, and the drivers, due to the time interval required for the transition of the integrating capacitor to the threshold level. The aim of the invention is to improve the accuracy of the conversion. This goal is achieved by the fact that, according to the method of converting alternating current into hours, utah, which involves integrating the input signal to one of

two threshold levels corresponding to the two polarities of the input signal, and the formation of standard current pulses of balancing polarity at the moments of reaching the threshold level and balancing the input signal by a sequence of standard current pulses, fix the integration points of the input signal to the third threshold level between the first two, and, at the moments of the first after the formation of the reference impulse, the output of the third threshold level is reached; output; iiiHe; nnyh current pulses alternating polarity output pulse after a subsequent output pulse is formed for odd and do not form an even number of the reference current pulse.

The goal is also achieved by the fact that the converter; alternating current into a frequency containing the first and second comparators, the first inputs of which are connected to the integrating capacitor, and the second inputs respectively, to the first and second sources of the reference voltage, and a generator of pulses of reference duration, the first and second outputs of which are connected respectively to the first and second inputs of the reversible pulse generator of the reference current, the third comparator is entered, the first input of which is connected to the integrating capacitor, and the second to the third source of the reference voltage. Shaper, the input of which is connected to the output of the third comparator, one-shot, the output of which is connected to the inverted and inverted outputs of the driver through differentiating circuits and diodes, first and second RS-triggers, first, second and third elements OR, first, second, third, fourth, p the second and sixth elements AND, the counting trigger and the element OR NOT, and the output of the one-shot is connected to the first input of the third element AND, the first output of the pulse generator of the reference duration is connected to the S input of the first RS trigger, h Through the second element OR to the R-input of the second RS flip-flop and to the second input of the second element AND, and the second output to the S-input of the second RS-flip-flop, through the first element OR to the R-input of the first RS-flip-flop and to the second input of the first And, and both outputs of the pulse generator of the reference duration are connected via the OR-NOT element to the second input of the third element AND, the first and fourth elements AND are connected by the first inputs to the output of the first RS flip-flop, the second and fifth elements AND are connected by the first inputs

to the output of the second RS flip-flop, the output of the third element I is connected to the second input of the sixth element I and to the R input of the counting trigger, the inverted output of which is connected to 5 the first input of the sixth element AND, and the counting input through the third element OR to the outputs of the first and The second elements And, the fourth and fifth elements And connected by the second inputs

Q to the output of the sixth element AND, the output of the fourth element AND is connected to the first output bus and through the first element OR to the R input of the first RS trigger, and the output of the Iko's second element to the second output bus and through the second element OR to the R input of the second RS trigger .

 Figure 1 shows the functional electrical circuit of the device; Fig. 2 shows timing diagrams explaining the method and describing the operation of the device.

The device contains an input bus 1, the first and second Comparators 2 and 3,

5 first inputs of which are connected to

integrating capacitor 4, and the second inputs - to the sources of the reference voltage 5.6, the pulse generator of the reference duration 7, the first and second outputs of which are connected to the control inputs of the reverse current pulse generator of the reference current 8, the third comparator 9, the driver 10, the one-shot 11, the first and second RS-triggers 12 and 13, the first, second

 and the third OR elements (14–16 respectively, the first, second, third, fourth, fifth, and sixth AND elements (17–22 respectively), the counting trigger 23, and the OR-PE element

0 24. At the same time, the third comparator 9 is connected by the first input to the integrating condensate 4, the second input to the source of the reference voltage 25, and the output to the input of the driver

e 10, the non-inverted and inverted outputs of which through differentiating circuits 26,27 and diodes 28,29 are connected to the input of a single-oscillator 11 connected by its output to the first input of the third element AND 19. The first output of the pulse generator of the reference duration 7 is connected to the S-echo the first RS-flip-flop 12, through the second element OR 15 to the R-BXOD of the second RS-flip-flop 13 and to the second input of the second element I 18. The second output-of the pulse generator of reference duration 7 is connected to S-Bxc "y of the second RS-flip-flop 13, through the first element OR 14 to the R-BXO0 remote control of the first RS- rigger 12 and to the second input of the first AND gate 17 and the two outputs of the reference pulse duration generator 7 via the OR-NO element 24 are bonded to the second

5 input of the third element And 19 .. The first and fourth elements And (17 and 20) are connected with their first inputs to the output of the first RS-flip-flop

12, second and fifth elements And (18

and 21) are connected by their first inputs to the output of the second RS flip-flop.

13. The output of the third element And 19 is connected with the second input of the sixth element And 22 and with the R input of the counting trigger 23, the inverted output of which is connected to the first input of the sixth element And 22, and the counting input through the third element OR 16. The second elements And 17 and 18. The fourth and fifth elements And 20 and 21 are each connected by their second input to the output of the sixth element And 22, the output of the fourth element And 20 is connected to the first output terminal 30 and through the first element OR 14 to the R-input the first RS-flip-flop 12, and the output of the p element And 21 - to the second in output terminals 31 and 15 through IL vtoroyelement to R-input of the second. RS flip-flop 13.

The device works as follows.

Before starting work, RS-flip-flops 12 and 13 and counting flip-flop 23 are set to the initial state by supplying single signals to their R-inputs (reset circuit is not shown in fig. 1 in the initial state). The input alternating current (FIG. 2a) is fed to the integral capacitor 4. When the voltage on the integrating capacitor 4 reaches the levels E, or E, the comparator 2 or 3 is triggered. The signal from the comparator output goes to the triggering output of the generator with a duration of 7, ac outputs of the latter, to the control inputs of the reversing generator of pulses of the reference current 8, which outputs balancing ethshonny impulses of the corresponding sign (figv). In this case, the voltage of the integrating capacitor is measured within the extreme levels of EE (Fig. 26). When passing the current, e; w on the integrating capacitor 4 through the middle level Еср, the third comparator 9 triggered by the driver 10 (for example, a Schmidt trigger type), we produce a rectangular nagging corresponding to the polarity of the difference signal of the third comparator (Fig. 2d), and at the other output, the inverse voltage is applied to the angular voltage. Each time the output voltage levels of the driver 10, the negative ont of one of the inverter output voltages of the gate driver, pass through the differentiating circuit 26 (27) and the diode 28 (29.) starts

one-shot 11 (figd). Each chick pulse from the output of the one-shot indicates that the voltage passes through the middle level, and thus the fixing operation is performed: 5 specified moments in accordance with the proposed method. Output pulses are generated taking into account the polarity of the current.

Let the input current have a positive polarity, and its integral value: increase. from the average level of the first extreme level E,. Then the first comparator 2 is triggered, the generator 7 outputs a pulse of the reference duration at its first output, the pulse generator of the reference current 8 outputs the corresponding balancing current pulse, the pulse from the output of the generator 7 simultaneously arrives at the S input of the first RS flip-flop 12 and through the second element OR 15 to the R input of the second RS flip-flop 13. In the process of a reference voltage drop on the integrating capacitor 4, it passes

5 through the middle level, the one-shot 11 produces a pulse, but it does not pass through the third element AND 19, since the second input of the latter is fed through the AND-NO element 24 to prevent the third signal during the entire duration of the reference pulse. At the end of the reference pulse, the first RS flip-flop 12 goes into one state. Second RS trigger 13

is in zero state. After

the reference voltage drop on the integrating capacitor rises from a value below the average level of Er, and when the average level is reached, the one-shot 11 is triggered,

the signal from the output of which passes through the third element I 19 and further to the second input of the Shlst element TL 22, the first input of which is supplied with a single signal from the inverse output

counting trigger 23.

From the output of the sixth elelyunt And 22 signal arrives at the second input of the fourth element And 20 and passes

on its output, since a single signal is fed to its first input from the first RS flip-flop 12. Thus, the pulse from the output of the one-shot 11 passes to the output 30, from where it goes through the element

OR 14 to the R input of the first RS flip-flop 12, transfer it to the zero state. The process then repeats.

In this way, the operation is performed on the first after the

acting on the reference impulse-passing voltage on the integrating capacitor through the middle level. A sign of a positive polarity is the appearance of an output pulse: and at output 30. At a negative input current, the voltage on the integrating capacitor decreases until it reaches the second extreme level, E, the second comparator 3 is triggered, the pulse generator 7 gives a forbidden signal to the second the input of the element AND 19 through the element OR-NB 24. After the end of the reference pulse, the voltage on the integrating capacitor is above the average level, the second RS flip-flop 13 goes into a single state. The reference pulse also arrives at the R input of the first RS flip-flop 12 through the OR 14 element and confirms its zero state. Next, the voltage on the integrating capacitor decreases to an average level, the third comparator 9 is triggered, and the pulse from the output of the one-shot 11 passes to the second output terminals 31 through the third element And 19, the sixth element And 22 and the fifth element And 21. At the same time allowing signals come from the output and the element OR-NOT 24 to the second input of the third element And 19, from the inverse output of the counting trigger 23 to the first input of the sixth Eleme, Nta K. 2 2 and from the output of the second trigger 13 to the first input of the second element I 21. The impulse from the output terminal 31 through the element 15 arrives at the R input of the second three hera 13, and the voltage at the last output takes the value logical zero. Consider the operation of the converter when changing the sign of the input current. After forming a next pulse at the first output 30, corresponding to a positive input current, let the current change direction to negative. In one case, the voltage on the integrating capacitor, not reaching the extreme level, returns to the middle level again (Fig. 26, section 1), or there may be repeated intersections of the average level. At the one-shot output, there are several pulses at the Wits, however, they will not go to the converter outputs, since the first input of the fourth element And 20 produces zero voltage from the output of the first R-flip-flop, set to zero by the last output pulse, sent to output 30, and the second RS trigger is also in the zero state, which prohibits the passage of output pulses to the second output bus 31. Thus, one of the operations of the proposed method, consisting in extracting the first after air (GSTV moment of voltage passing through the middle level. An output pulse with a negative polarity sign is formed after the reference reset from the second extreme level at the time of the average voltage crossing the level. In another case, the voltage on the integrating capacitor reached the first extreme level, the reference reset occurred, the first RS the trigger turned into a single state and remembered positive polarity. However, after a reference reset, the voltage due to a change in the sign of the current did not reach the average level to vary in the negative direction and has reached a second extreme levels (Figure 26, section ii). After the comparator 3 triggers, a second pulse is generated at the second output of the generator 7, which is fed to the S input of the second RS flip-flop 13 and through the OR 14 element to the R input of the first RS flip-flop and also passes through the first OR 17 element, to the first input which is fed a single signal from the output of the first RS flip-flop 12. The signal from the output of the element AND 17 through the element OR 16 is fed to the counting input of the trigger 23, the purpose of which is to determine the parity of the total number of alternating polarity reference pulses. The considered pulse at the counting input of the trigger 23 is the second ethcone pulse, i.e., the counting pulse (the first was a reference pulse of opposite polarity before the current sign changed), after passing through the inverse output of the counting trigger 23, the logical zero voltage is applied to the first the input of the sixth element is AND 22; Upon the expiration of the pulse arriving from: the second output of the reference generator 7, the second RS flip-flop is set to one, and the first RS flip-flop is set to zero. If the voltage on the integrating capacitor 4 now reaches the average level, then the pulse from the one-shot 11 passes through the third element 19 and 19 but does not pass through the sixth element 22 and to the output terminals (the case of an even number of pulses). If the voltage on the integrating capacitor 4 does not reach the average level, and due to a secondary change in the sign of the input current reaches the first level, then the comparator 2 will work, a pulse will be generated at the first output of the generator 7, which is fed to the second input of the second I-18 element. Since the first input of the last receives a single signal from the second RS flip-flop 13, the pulse passes to the output of the element AND 18 and through the element OR 16 to the counting input of the trigger 23, as a result of which its inverse output establishes a voltage passing units

the next output pulse through the sixth element OR 22, the fourth element OR 20 to the output terminal 30 in case the voltage is integrated. The capacitor reaches an average level (the case of an odd number of alternating different polarity reference pulses).

Thus, this device implements the proposed method of converting alternating current into frequency.

Since the moments of the appearance of the output pulses correspond to the moments when the voltage on the capacitor 4 reaches the average level regardless of the polarity of the input signal, the value of the period of the output frequency during which the polarity of the input current changes, does not affect the capacitance of the capacitor 4 and levels E and Ej. In this way, an increase in conversion accuracy is achieved.

Claims (2)

1. A method of converting alternating current into a frequency, which consists in integrating the input signal to one of two threshold levels corresponding to the two polarities of the input signal, forcing reference current pulses of counterbalancing polarity at the moments of reaching the threshold level and balancing the input signal with a sequence of standard current pulses , characterized in that, in order to increase the accuracy of the conversion, the integration moments of the input signal are fixed to the third threshold level found 5 between the first two, and at the moments of the first after the formation of the reference impulse, the output impulses reach the third threshold level, and if our reference impulses alternate polarity after some output impulse, the output impulse is generated at odd and not even at the number of current reference pulses. 2. The alternating current-to-frequency converter, which contains the first and second comparators, the first inputs of which are connected to the integrating capacitor, and the second inputs, respectively, to the first and second reference voltage sources, and the pulse generator is a standard. duration, the first and second outputs of which are connected, respectively, to the first and second inputs of the reversible reference current pulse generator, which, in order to improve the accuracy of the conversion, a third comparator is entered into it , the first input of which is connected to the integrating capacitor, and the second to the third source of the reference voltage, driver, input. which is connected to the output of the third comparator, a one-shot, the input of which is connected to the non-inverted and inverted outputs of the driver through differentiating circuits and diodes, the first and second RS-triggers, the first, second and third elements OR, first, second, third, fourth, fifth and the sixth And elements, the counting trigger and the OR-NOT element, the one-shot output is connected to the first 0 (The third input of the third element AND, the first output of the Pulse Generator of the reference duration is connected to the S input of the first RS-trigger, ente OR- to the R-input of the second RS-flip-flop and to the second input of the second element AND, and the second output to the S-input of the second RS-flip-flop, through the first element OR to H-in the first RS-flip-flop and to the second input of the first element AND and both outputs of the pulse generator of the reference duration are connected through the OR-NOT element to the second input of the third element AND, the first and fourth elements AND are connected by the first inputs to the output of the first RS flip-flop, the second and fifth elements And are connected by the first inputs to the output of the second RS- trigger, the output of the third element And is connected to BTOfftJM input of the sixth element And with the R-input of the counting trigger, the inverted output of which is connected to the first input of the sixth And element, and the counting output through the third element OR - to the outputs 5 of the first and second elements And, the fourth and fifth elements And connected the second inputs to the output of the sixth element And, the output of the fourth element And connected to the first output shil n & through the first element OR to the R input of the first RS trigger and the output of the fifth AND element to the second output bus and through the second OR element to the R input of the second RS trigger. Information sources, taken into account in the examination 1. US patent 3256426, CL 235-183, 1969. 2. Patent CIilA 3877020, cl. 340-347, 1975. tCf fz p (1 I and p i J p 00 it.