SU1182676A1 - Device for converting pulse repetition frequency to number - Google Patents

Abstract

A DEVICE FOR CONVERSION OF THE FREQUENCY OF THE PULSE COLLECTION IN THE CODE, containing a block for forming a time interval, a coincidence element, a shaper of clock pulses connected in series with a pulse counter, a block of elements AND, accumulating cmmator and a shift register, with the input of the block of forming a time interval connected to a unit. , and the output of the time interval shaping unit is connected to the control input of the coincident element and the control input of the clock pulse generator. owls, first. the output of which is connected to the first clock input of the accumulating adder, the second input of which is connected to the No code feed bus, the second input of the pulse clock generator is connected to the second clock input of the accumulator of the accumulator and the clock input of the shift register, the information input of which is connected to the output of the accumulating adder and the control of the shift register Let us input the block element. And, and the input of the match element is connected to the pulse bus ,. the reference frequency and to the clock clock pulse input, characterized in that, in order to increase the conversion accuracy, an inverter, an additional match element and an RS flip-flop, whose S input is connected to the output of the main match element, and the R input are connected, are entered into it to the output of the additional element of the coincidence element, the control input of which is connected to the output of the time interval generation unit, the information input of the additional element of the match is connected to the output of the inverter whose input is connected to not the reference 00 frequency, the single output of the RS flip-flop is connected to the counting input of the pulse counter, and to the low-order input of the I block, and the signal bus Start is connected to the second O) input of the time interval shaping unit, the setting input of the RS-trigger and the installation input of the pulse counter.

Description

The invention relates to automation and computer technology and is intended to convert a pulse frequency into a 1GRV code.

FIG. 1 is a diagram of a pre-set device in FIG. 2, a time diagram of the operation of the device.

The purpose of the invention is to improve the accuracy of the conversion by reducing the quantization error,

A device for converting a pulse following frequency into a code (FIG. 1) contains a block 1 for forming a time interval, a coincidence element 2, a shaper of 3 clocks, a counter of 4 pulses, a block of 5 elements, and an accumulator 6, a shift register 7, an inverter 8 , additional match element 9, RS flip-flop 10, Start signal bus 11, reference frequency pulse bus 12 — bus 13 of convertible frequency pulses, input code 14 of code Nj, 5 with the output of block 1 connected to the input of element 9, another input of which Inverter 8 is connected 3 builder, another input coupled to the output of element 1 and 2 whose output is connected to the input of flip-flop 10 connected to the element 9, the counter unit 4 and 5, the other inputs of which are connected to an adder 6 and 7 register; the outputs of the imaging unit 3 are connected to the inputs of the adder 6 and register 7,

FIG. 2prints you follow. cheny; signal and on the bus 13 pulses of the converted frequency | signal B on bus 11; the signal in bus 12 of the reference frequency signal f; the signal g in the code of the block 1 forming the time interval; signal E at the single output of the RS flip-flop Yu; signal e at the first output form. body 3 clock pulses; signal w at the second output of the imager 3 clock pulses.

The device works as follows.

When the signal is applied to the Start 11 bus (Fig. 25), the initial (zero) state of the block 1 is formed for forming a time interval. Counter 4, RS-flip-flop 10 On the leading edge of the signal of the converted frequency f ,, fed through the bus 13 after the start signal, block 1 generates the time interval t (firm, 2 g), equal to the periods of the converted frequency f (figure 2 ") The leading edge of the signal t opens element 2 and element 9, and the control S and R inputs of the trigger 10 begin to receive pulses of the reference frequency f (Fig 2 in), and the S-inputs pulses through the element. 2 ,. and to the R input through an inverter 8 and element 9, with the result that when the pulse frequency of the reference frequency is 2, the trigger 10 is in state 1, the first half of the frequency period f "state O" is in the second half of the half-period frequency f (Fig , 2 3), Counter 4, the counting input of which is connected to the unit 3 at the output of the RS trigger 11, counts the number of full periods of frequency f during time t, and the trigger 10 fixes each half period of the reference frequency f during the same time t, At the time of the end of the time interval t. elements 2 and 9 are closed, and trigger 10 remains in the state in which it nahodils immediately before the end of the time interval t-, and the counter 4 at that

I

n-fyr

the moment is fixed N

x

proportional to the number of full periods of the frequency fj. . Thus, on trigger 10 and counter 4 at the time of the end of the measurement interval

t recorded code N 5 proportional to the period of the measured frequency f and equal to the integer number of half periods of the reference frequency time t. After the end of the time interval, the shaper of 3 clock pulses is activated and using the block 5, the accumulating adder 6 and the shift register 7, the conversion of the period code begins

N.J. in frequency code f

according to the formula

 l1 x --N - N /.

The conversion is carried out as follows: The accumulating adder 6 raises the number NU 2nfj.p on the bus. Since the number is N 7 O, the sign bit on the accumulator of the drinking adder 6 is in the unit state and the control of the unit is fed to the control input of the unit 5. Under the action of this potential, block 5 inverts the N .. code coming from the output of counter 4 and trigger 10 (low bit) and transmits this inverse code N to the input of accumulating adder 6. Next, shaper 3 forms the first clock t1, resulting in Sum 1 - 1 6, the NIJ code is added with the inverse code N. After the end of the first clock cycle T, the sum of the numbers recorded is N, maybe., p, which is positive or negative. The connection of the sign bit of the adder 6 with the low bit of the shift register 7 is completed so that, at the moment when the shaper 3 generates a shift step of 12, the inversion of the sign bit status of the adder 6 is recorded at the lower bit of the register 7 6 and register 7 for one bit in the direction of older bits. This completes the first cycle of converting the N code to the f code and, as a result, register 7 has the value of the first 764 N written. Depending on the sign of this number, the control input of the 5 noci-yapa unit is either the potential of a logical unit or the potential of a zero. In the first case, block 5 inverts the code N., in the second case, the direct code of the number N is transmitted to the adder 6. Thereafter, the former 3 forms the second two clock cycles T1 and T2, resulting in the second code bit f, etc. The number of cycles (conversion of the N code into the code is taken depending on the required conversion accuracy. Most often the number of conversion cycles is equal to the number of m bits of the counter 4. After the completion of all m conversion cycles, in the shift register 7 the converted frequency code f is written. The error of the folding is from the conversion error in the adder and the quantization error. The conversion error can actually be reduced to zero by increasing the number of conversion cycles.m. The quantization error by Roman Neni flip-flop 10 in the Offering

0USJ

1 code / x

FIG. 2

Claims (1)

A DEVICE FOR CONVERTING FREQUENCY OF FOLLOWING PULSE FOLLOWING TO A CODE, comprising a time interval generating unit, a coincidence element, a pulse shaper, pulse counter connected in series, an AND block, accumulating an adder and a shift register, the input of the time interval generating unit being connected to the frequency conversion pulse bus connected to and the output of the time interval forming unit is connected to the control input of the coincidence element and the control input of the clock generator, the output whose output is connected to the first clock input of the accumulating adder, the second input of which is connected to the N code supply bus, the second output of the pulse shaper is connected to the second clock input of the accumulating adder and the clock input of the shift register, the information input of which is connected to the output of the accumulating adder and. the control input of the block of AND elements, and the input of the coincidence element is connected to the pulse bus, the reference. frequency and to the input of the clock pulse generator, characterized in that, in order to increase the conversion accuracy, an inverter, an additional coincidence element and an RS-trigger are introduced into it, the S-input of which is connected to the output of the main coincidence element, and the R-input is connected to the output additional coincidence element, the control input of which is connected to the output of the time interval forming unit, the information input of the additional coincidence element is connected to the output of the inverter, the input of which is connected to the reference frequency bus , the single output of the RS-flip-flop is connected to the counting input of the pulse counter, and to the input of the least significant bit of the block of elements And, and the bus signal “Start” is connected to the second input of the block for the formation of the Time Interval, the installation input of the RS-trigger and the installation input of the pulse counter. SU, 1182676 1182676 2