SU1363481A1 - Code converter - Google Patents

Abstract

The invention relates to digital computing and can be used in the construction of code converters. The aim of the invention is to expand the class of tasks to be solved by providing the possibility of inverse transformation. The goal is achieved by the fact that a switch 11 is entered into the converter containing the first and second counters 3,4, comparison circuit 5, register 6, pulse generator 7 ", first and second elements 8,9, whose inputs are connected to the outputs of the first and the second counters, and the outputs - with the inputs of the comparison and register, respectively, 1 Il. (L SLE O) with 4; 00

Description

The invention relates to digital computing and can be used in the construction of code converters.

The purpose of the invention is to expand the class of tasks to be accomplished by providing an inverse transformation.

The drawing shows the functional diagram of the code converter

The converter contains information inputs 1, installation inputs 2, first 3 and second 4 counters, comparison circuit 5, register 6, pulse generator 7, first 8 and second 9 elements And, outputs 10, switch 11, and control input 12.

Converter codes works as follows.

Prior to operation, counters 3 and 4, counting respectively in the first and second codes at input 2, are set to zero. If it is necessary to convert the first code to the second, you need to apply a single potential to the control input 12, which connects the outputs of the counter 3 to the comparison circuit 5 via the switch 11, and the outputs of the counter 4 to the register 6. If necessary, the second code is converted to the first one at input 12 control zero potential, which connects the outputs of the counter 3 to the register 6 through the switch 11, and the outputs of the counter 4 to the comparison circuit 5. In the absence of convertible code 1 at inputs 1 and 2 of the comparison circuit 5, the signals of logic level zero are set, and at the third output - a signal of logical unit which is fed to the synchronization input of register 6 memory, while register 6 is written From counter 3 or 4, depending on the signal at input 12, zero signals, which are also set at output 10.

The code to be converted is fed to the inputs of the comparison circuit 5. In this case, if the conversion code is not zero, the logic unit level signal is set at the first output of the comparison circuit 5, and the logic level zero signals are set at the other outputs.

The signal level of the logical zero from the output of the Less comparison circuit 5 prohibits the passage of pulses from the generator 7 through the element 9,

the signal level of the logical unit from the output greater than the comparison circuit 5 permits the passage of pulses from

generator 7 through the element And 8 to -1 / „

the first inputs of counters 3 and 4. When

when the counters reach 3 numbers equal to the received convertible code, the output is equal to circuit 5 of the comparison

the signal of the level of the logical unit is set, and the output of the Greater output is the signal of the level of the logical zero, which prohibits further passage of pulses through the element

And 8 to counters 3 and 4. At the outputs of the counter 4, counting in the second code, the input number 1 is set in the transformed code, which from the outputs of the counter

4, by the signal of the logical unit from the output Equal to the comparison circuit 5, is rewritten into register 6, the outputs of which and the outputs 10 of the converter are set to

the converted signal in the second code.

When changing the value of the code to be converted, for example, to a value less than the previous one,

the output of the Smaller Comparison Circuit 5 is set to a signal of a logical unit, and on the remaining outputs a signal of the level of a logical zero. In this case, passing through the And 9 element pulses from the generator 7 to the second inputs of counters 3 and 4. The contents of counters 3 and 4 start to decrease, and when the counter reaches 3 a state equal to the code value at input 1, the output is Smaller than comparison circuit 5 the signal is set to a logic level zero, the passage of pulses from the generator 7 through the element And 9 stops. At the output of Equal circuit 5, a comparison is established with a level signal of a logical unit that records the state of counter 4 in a new, converted code in register 6.

Claims (1)

Formula of Invention | A code converter containing the first and second counters of the first and second elements AND, a register, a comparison circuit, a pulse generator, the output of which is connected to the first inputs of the first and second elements AND, the second inputs of which are connected respectively to the outputs More and Less comparison, the Output Equal to which is connected to the register entry input, the outputs of which are the outputs of the converter, whose information inputs are connected to the first group of inputs of the comparison circuit, the output of the first element I is connected to the increment inputs of the first and second counters, the inputs of decrement I of which connected to the output of the second element And, the input of the installation of the Converter is connected to the reset inputs of the first and second counters, about t - Editor A. Ogar Order 6380/54 Compiled by M.Arshavsky Tehred L. Serdyukova Circulation 900 VNIISH State Committee of the USSR .on matters of inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 63481 characterized by the fact that, in order to expand the class of problems to be solved by providing the opposite g transformation, a switch is entered into it, the first and second groups, whose inputs are connected to the output groups of the first and second counters, respectively, the first group of outputs of the switch, are connected to the second group of inputs of the comparison circuit, the information inputs of the register are connected to the second group of outputs of the switch that controls whose entrance is 1G control input converter. Proofreader MoMaximishinets Subscription