SU1316051A1 - Static register - Google Patents

Abstract

The invention relates to computing and can be used in information storage devices. The aim of the invention is to expand the scope of the register by providing reception of information in forward and reverse codes from several directions. For this, two inverters and AND elements are introduced into the register, which are used to form the receive control signals, and a trigger is used that allows the reception of information from several directions. 1 il. oo o5 o ate

Description

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The invention relates to computing and can be used in information storage devices.

The aim of the invention is to expand the scope of the register by providing reception of information in forward and reverse codes from several directions.

The drawing shows a static register diagram.

The register contains n bits 1. Each bit consists of trigger 2 and the four elements NAND 3-6. The register also includes two inverters 7 and 8 and four elements AND 9-12. The drawing shows the inputs 13 and 14 for controlling the phase of receiving information, the inputs 15 and 16 of the receiving direction, information inputs 17 and 18, and outputs 19 of the register. Triggers 2 are made on the elements AND-NOT 20 and 21.

The operation of the static register is as follows.

To write a direct input code to the static register, which is fed to inputs 17 or 18, a logical O (pulse signal) is sent to the input 13 of the receiving phase control, and a pulse signal is sent to the first inputs of the And 9 and 10 elements - 1 and the third R-inputs of the triggers are logical O, and all triggers are reset.

To write to the code register, for example, from inputs 17 to input 15 of the receiving direction, logical 1 is fed, which is fed to the second input | 1 elements AND 10 and 12, At the same time, at the output of the element AND 10, a logical 1 signal appears, which arrives at the first inputs of the AND-NE 4 elements of each bit.

As a result of this, for example, logical 1 from input 17 in the NAND element 4 is converted into a logical O, which is fed to the S input of the trigger 2, and logical 1 is set at its output. If there is a logical O, 17 4 does not change its state, which corresponds to a record in bit 1 of the logical O. register. Elements AND 9-12, the first 7 and second 8 inverters, in combination with AND-NOT elements 3-6, are used as delay elements for a time equal to

12

the trigger time 2. In case the reverse code is required to be recorded from the inputs 17, it is necessary to send a pulse signal

About to input 14 controls the phase of reception. In this case, similarly, the triggers are first set to one state and, depending on the code at inputs 17, the output of the AND-HE element 6 is set to either logical O, if logical input is present at input 17. or - vice versa, which leads to the establishment of trigger 2 in O or in 1

respectively. I

When writing to the code register from inputs 18, signal 1 is applied to input 16 of the receiving direction. In this case, a change in the state of the trigger is made through the elements AND-NOT 3 or 5.

Claims (1)

Invention Formula A static register containing in each discharge a trigger and four NAND elements, with the first and second S inputs of the trigger connected to the outputs of the first and second AND elements, the first and second R inputs with the outputs of the third and fourth I elements. NOT, and the output is an information output of the register, which is because in order to expand the scope of the register by providing reception of information in forward and reverse codes from several directions, two inverters and four elements I are entered into it, the outputs which are connected to the first E inputs of the corresponding AND-NO elements each bit, the first and third inputs of the first, second and chetver45 In addition, the elements of AND are respectively the inputs of the register reception direction, the second inputs of the first and second, third and fourth elements of AND are connected respectively to the outputs of the first and second inverters, whose inputs are connected to the third R and S inputs of each bit, respectively, and the control inputs of the reception phase in the register, The second inputs of the first and third, second and fourth elements of the NAND of each bit are information inputs of the register. 13 o Editor A.Vorovich Compiled by A.Derugin Tehred A.Kravchuk Order 2370/55 Circulation 589 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 Proofreader A. Obruchar