SU1677867A1 - Bidirectional counting device - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation, telemechanics and instrument making as a binary reversing counter with programmable weighting factors of bits. The purpose of the invention — extending the functionality — is achieved by introducing switches 2.1-2.3, control buses 7.1-7.3, a generator of 3 write pulses containing an AND-NE element 8, an inverter 9, drivers 14-14 and having an output. The device also It contains a t-bit binary counter 1, an input bus 4, a reverse control bus 5, a reset bus 10. In the proposed device, the software modifies the counting module by blocking the lower bits of counter 1 and ensuring the functioning of the higher bits of counter 1 as the lower bits. 1 hp f-ly, 1 ill.

Description

The invention relates to a pulse technique and can be used in automation, telemechanics and instrumentation as a binary reversible counter with programmable discharge weights.

The purpose of the invention is the expansion of functionality is achieved through the introduction of new design features that provide a software change in the module account and change the weight coefficients of the discharges.

The drawing shows a structural diagram of a reversible counting device.

The drawing shows a t-bit binary reverse counter 1, η switches 2.1-2.3, driver 3 write pulses, input bus 4, bus 5 control reverse, output 6 of driver 3 write pulses, η control buses 7.1-7.3, AND-NOT 8 element , the inverter 9 of the shaper 3 of the recording pulses, the reset bus 10, the first, second, third and fourth shapers 11-14 of the shaper 3 of the recording pulses.

An input bus 4, a reset bus 10, and a reverse control bus are connected respectively to a clock input, a reset input, and a reverse control input of a t-bit binary counter; the first, second, third inputs and output 6 of the shaper 3 are connected respectively to the reverse control bus 5, the input bus 4, the reset bus 10, and the load control input of the m-bit binary counter; control buses 7.1-7.3 are connected respectively to the control inputs of switches 2.1-2.3, the first inputs of which, starting from switch 2.1, are connected respectively to the outputs of the bits of the binary reversible counter 1, starting from the first bit, the second inputs of switches 2.1-2.3 are connected to the bus 5 reverse control; the outputs of switches 2.1-2.3, starting with switch 2.1, are connected respectively to the information inputs of the bits, starting with the first binary counter counter 1, the information input of each of the other bits of which is connected to the output of the same bit of the binary counter counter 1.

The second, third and first inputs of the shaper 3 are connected through shapers 11-13, respectively, with the first, second, third inputs of the AND-NOT 8 element, the output of which is connected to the output 6 of the shaper 3 of the recording pulses, the first input of which is connected to the fourth through the inverter and shaper 14 input element INE 8.

As shapers 11-14, differential chains can be used.

The device bits from the first to the nth are controllable, and the senior bits are uncontrollable. Each controlled bit is formed by the corresponding bit of the counter 1 and the corresponding switch 2. Each such bit is controlled via the corresponding bus 7. The controlled bit is in the on (counting) mode when a logical level arrives at the corresponding bus 7, under which the corresponding switch 2 connects the output of the corresponding discharge of counter 1 with its information input. Otherwise, the discharge is in the off (passive) mode, while the corresponding switch 2 connects the information input of the corresponding discharge with the signal on the reverse control bus 5.

Uncontrolled high-order bits of counter 1 always work in counting mode and differ from the bits of a conventional binary reverse counter only in that the output of each of them is connected to its information input.

Shaper 3 start pulses works as follows.

The pulse at the output of the shaper 3 appears every time after the counter 1 is triggered from each next clock pulse on bus 4, but until the next clock pulse arrives, after the logical signal level value acting on bus 5 is reversed, after the device is reset on bus 10 .

After the appearance of a pulse at the output 6 of the shaper 3, the states of all uncontrolled bits of the counter 1 do not change, since the information inputs of these bits are connected to their outputs. The states of those controlled sections of the device that are in the on mode also do not change, since in this mode the channel of switch 2 included in each of these sections (bits) is turned on, which connects the information input of the corresponding bit of counter 1 to its output. In all disconnected managed sections, the logical level is written from the bus 5 to the second inputs of the switches 2.1-2.3 (logical 1 in addition mode, logical ”0 in subtraction mode).

The device operates as follows.

Assume that all managed sections of the device are in the on state (counting mode). Then the device is a regular binary counter. After the arrival of each pulse on the bus 4, the counter 1 changes its state and after the end of the transient processes, a pulse appears at the output of the shaper 3, which transfers its previous state to the counter.

Let part of the control sections, for example, the two youngest, be in the off state. Let us also assume that the device operates in the addition mode (i.e., logical 1 is present on bus 5) and that in the initial state, the outputs of the bits of counter 1 present a code 110 ... 0. Then, with the arrival of a pulse on bus 4, the code 0010 ... O is set at the outputs of counter 1 (counter 1 is triggered on the positive edge of the positive clock). After the end of the first pulse on the bus 4 at the output 6 of the shaper 3 appears a pulse, which writes the code 1110 ... 0 to the counter. After the second pulse arrives on bus 4, a code 1 will be present in counter 1

11010 ... 0. Similarly, the device will function with the arrival on bus 4 of each subsequent pulse.

Thus, in this example, the counting device is a 2 ^t_2 bit reversible binary counter, the ^{least significant} bit of which (start section) is the third bit of counter 1. And the highest is the last bit of counter 1. In this case, the third bit of counter 1 will have a binary weight of 2 °.

In the subtraction mode, the outputs of the switches 2.1-2.2 (unchanged) and the outputs of the two least significant bits of counter 1 (before the arrival of the clock pulse) will have level 0 ”, then the clock signal on bus 4 will set the two least significant bits first to 1, and after the end clock pulse - at 0.

When a reset pulse is received via bus 10, a zero combination is established at the outputs of all bits. In the mode of subtracting the status of the bits of the counter 1 after the end of the pulse on the bus 10 do not change. In the addition mode and in the presence of disconnected sections at the end of the pulse on the bus 10, the counter 1 switches to the state 1 ... 10 ... 0, since the pulse from the output of the shaper 3 is formed at the end of the pulse on the bus 10.

When changing the account mode, i.e. when the potential on bus 5 changes, the logical levels at the outputs of disconnected sections change to the opposite. At the outputs of the remaining bits, the states do not change. The pulse generated by the shaper 3 writes information from the device outputs (outputs of the switches 2 and outputs of the senior bits) into the bits of the counter 1, ensuring its readiness for operation in a given counting mode.

Claims (2)

Claim 1. A reversible counting device comprising an input bus, a reverse control bus, a reset bus, and an m-bit binary counter having a load control input, a reset input bus, and a reverse control bus are connected respectively to a clock input, a reset input, and an rn-bit binary reverse control input a reverse counter, characterized in that, in order to expand the functionality, η control buses (where η <m), η switches and a write pulse shaper are introduced into it, first, second, third input and the output of which is connected respectively to the reverse control bus, to the input bus, to the reset bus, and to the load control input of the t-bit binary reverse counter, η control buses are connected respectively to the control inputs of η switches, the first inputs of which, starting from the first switch, connected respectively to the outputs of the bits of the binary reversible counter, starting from the first category, the second inputs of the switches are connected to the reverse control bus, the outputs of the n switches, starting from the first, are connected ootvetstvennoe input information bits, starting with the first binary down counter, an information input of each of the remaining bits connected to the output of the same digit binary down counter. 2. The device according to claim 1, wherein the recording pulse generator comprises an NAND element, an inverter and first, second, third and fourth drivers, the second, third and first inputs of the recording pulse generator are connected respectively through the first , the second and third shapers with the first, second and third inputs of the AND-NOT element, the output of which is connected to the output of the recording pulse shaper, the first input of which is connected through the inverter and the fourth shaper connected in series with the fourth input of the 14НЕ element.