SU1359888A1 - Pulse generator - Google Patents

Abstract

The invention can be used, for example, in telemetric systems, information transmission systems. The purpose of the invention is to expand the functionality of the generator. The device comprises a clock pulse generator 1, a trigger 2, an AND 5 element, an OR 6 element, a pulse counter 7, a puller for 8 pulses, and blocks 9 and 10 of comparison and control. The proposed functional connection of the elements of the device and the specific implementation of the control unit 10 ensures the formation of a pulse of any shape. 1 hp f-ly. 1 il. (L C & 0 ate from 00 00 00

Description

The invention relates to a pulse technique and can be used. Vaio in telemetry systems, information transfer systems and image synthesizers.

The aim of the invention is to enhance the functionality by forming single and cyclic pulses of sequences of any shape.

The drawing shows the functional diagram of the pulse generator. The pulse generator contains 1 clock pulse generator, trigger 2, bus 3 Start, bus 4 Stop, element 5, element OR 6, pulse counter 7, pulse driver 8, comparison unit 9 control unit 10, which contains a memory 11, counter 12 addresses, the OR element 13 and the input device 14, as well as the output bus 15, the output of the generator 1 is connected to the first input of the AND element 5, the second input of which is connected to the direct output of the trigger 2, the third input of which is connected to the bus 4, the bus 3 is connected to the second input of the trigger and to the input u OR 6, the other input of which is connected to the first output of the imaging unit 8, whose input is connected to the output of the counter 7, the subtracting input, the synchronizing input and the installation inputs of which are connected respectively to the output of the AND 5 element, the PW 6 and the device 11 of the block .10, - the second group of outputs of which is connected to the second group of inputs of block 9, the first group of inputs of which is connected to the bit outputs of counter 7, the inverse output of trigger 2 is connected to the first input of block 10, the first output of which It is connected to the first input of the trigger 2; in the control unit 10, the outputs of the input device 14 are connected to the information inputs and installation inputs of the storage device 11 and the address counter 12, the bit outputs of which are connected to the discharge inputs of the storage device 11, the first output of which is connected to the first input element OR 13.

The device works as follows.

In the initial state, the trigger 2 is in the zero state, and through the OR element 13 the counter 12 of the address of the block 10 is maintained in the zero state, while in the memory 11 the zero memory cell is selected. The memory word contains 2n + 2 bits, with the first bit containing information about the completion of a single sequence of pulses, the next n bits - about the period of the pair of pulses, the next n bits of the duration of the pulse (2n + 2) -th bit carries information about the completion of a cyclic sequence of pulses. Depending on the organization of the counter 7 and block 9, the follow-up period and the duration of the generated pulses can be encoded in a binary-decimal or binary code. The storage device 11c 2 cells allows you to respectively form a sequence of 2 pulses with a period of following any pair of pulses from 21 to 2 T and a duration of any pulse from T to (2 -1) T, where T is the period of the pulse of generator 1.

When a start pulse is applied to bus 3 via the OR 6 element, the recording of the period code T in the counter 7 is synchronized. The period code T arrives at the installation D inputs of the counter 7 along the buses of the first group of outputs of the block 10 (which are the outputs of the storage device 11), one - temporarily the trigger 2 goes into one state, thereby allowing the passage of pulses from generator 1 through element 5 to the subtracting input of counter 7. The state of counter 7 with the current cycle starts decreasing by 1. Block 9 compares status code audio the counter 7, entering it with the bit outputs of the counter and the pulse width code C supplied to the comparing unit 9 outputs a block group 10 (group memory 11 outputs).

At the output of block 9, a low level is formed if the status code

counter 7 is longer than the pulse duration code received from memory 11. As clock pulses arrive in

the number of T-V states of the counter 7 becomes equal to the long-nos code. J and the output of block 9 forms a high level. After passing another C clock from the generator 1, the counter 7 is reset and a loan signal is generated at its output, while the driver 8 generates forward and delayed pulses. The forward pulse increases the state of the counter 12 in block 10 on

and on the delayed pulse coming through the second input of the element OR 6 to the synchronizing input of the counter 7, a new period value of the generated pulses is recorded on the setting inputs of the counter 7 from the newly selected memory cell 11. The second inputs of the comparison unit 9 accordingly, a new code of the duration of the next generated pulse arrives. Next, the cycle of the generator is repeated.

The pulse generator can operate in three modes.

In the first mode, no recording is made in the first and (2p + 2) -th bits of the storage device 11, while the generator operates in a cyclic mode, forming repetitive sequences of 2 pulses.

The second mode of operation of the generator is ensured by writing the unit to the 1st bit of the Kth cell of the memory 11. In this case, after starting the generator, K pulses are formed and the operation stops.

The third mode of the generator occurs when the unit is recorded in the (2p + 2) -discharge of the i-th memory cell 11. After starting, the generator operates in a cyclic mode, forming repetitive sequences consisting of i pulses. Formula of the invention

Claims (2)

1. A pulse generator containing a clock pulse generator whose output is connected to the first input of an And element, the second input of which is connected to the forward output of a trigger, the output of the And element is connected to VNIIPI Order .6163 / 55 Circulation 900 Subscription Random polygons pr-tie, Uzhgorod, st. Project, 4 0 5 0 5 ABOUT five five 0 0 subtractive input pulse counter ,. the synchronization input of which is connected to the output of the OR element, the bit outputs of the pulse counter are connected to the first group of inputs of the comparison unit, the pulse driver, the control unit, the first output of which is connected to the first trigger input, so as to expand the function capacity of the pulse counter is connected to the input of the pulse former, the first output is. which is connected to the first input of the OR element, whose second input is connected to the second trigger input and to the Start bus, the third trigger input is connected to the Stop bus, the inverse trigger output is connected; To the first input of the control unit, the second input of which is connected to the second output of the pulse generator, The first group of outputs of the control unit is connected to the inputs of the pulse counter installation, the second group of outputs of the control unit is connected to the second group of inputs of the comparison unit. 2. The generator according to claim 1, characterized in that the control unit comprises a memory device, an address counter, an OR element and an input device, the first and second groups of outputs of which are connected to the information inputs of the memory device and the installation inputs of the address counter, respectively, the installation input zero state which is connected to the output of the OR element, the first input of which is connected to the first output of the storage device, the second output of which is the first output of the control unit, the address inputs of the storage memory The devices are connected to the bit outputs of the address counter, whose input is the second input of the control unit, the first and second groups of memory outputs are the first and second groups of outputs of the control unit, the second input of the OR element is the first input of the control unit.