SU754409A1 - Number comparing device - Google Patents

Description

The invention relates to automation and computing and can be used in digital systems of automatic control, in particular, in digital measuring devices.

A device for comparing decimal numbers with upper and lower tolerance limits on the principle of "less", "norm", "more", which is performed on mechanical elements, contains four diode array control triggers that convert decimal numbers into binary ones, which are compared on a diode one. comparison scheme [ΐ].

The disadvantage of this device is its complexity.

The closest in technical essence to the present invention is a device containing a counter, specifying the value of the monitored parameter in the decimal code (unit for issuing the monitored parameter), decade voltage divider, units for issuing the lower and upper 10

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it tolerances, the unit of comparison, consisting of nodes comparing the junior and senior bits. performed on three-position polarized relays, display unit [2].

The disadvantage of this device is low speed.

The purpose of the invention is to increase speed.

This goal is achieved by the fact that in the device containing blocks issuing numbers, unit comparison units, N dozens of comparison nodes, display unit, the outputs of the first, second and third issuing units are connected to the first, second and third informational ones: the inputs of the unit of comparison and comparison nodes, tens, the first and second outputs of the unit of comparison of units are connected to the first and second control inputs, respectively, of the first comparison node of tens, the first and second outputs of each ΐ -th comparison node of tens, dd <-1,2, ... (π -1) are connected to first and second upravlyayu3 754409

to the inputs () +1) –γο of the tens comparison node, the outputs of the ηth comparison node are connected to the inputs of the display unit, the comparison unit of units contains two OR elements, the comparison cell of the most severe discharge consisting of two AND elements and nine comparison cells, each of which consists of two elements And and element OR, with the first information inputs of the corresponding bits of the unit of comparison of units connected to the first inputs of the elements And cells of the comparison of the senior discharge and cells of the comparison, the second information inputs of the corresponding discharge The nodes of the node are connected to the first inputs of the second elements And the high-order comparison cells and comparison cells, the third information inputs of the corresponding bits of the node are connected to the second inputs of the High-level comparison cells> and the first inputs of the OR cells, the third high-level information input is connected to second ^! to the input of the element OR of the first cell of the comparison, the output of the element OR of each]. oh, where] = 1,2, ... 9 cells

comparison is connected to the second input of the element OR (] +1) -th cell of the comparison and with the second inputs of the elements AND

] th comparison cells, the outputs of the first elements AND the high-order comparison cells and the comparison cells are connected to the inputs of the first element. OR, the output of which is connected to the first output of the node, the outputs of the elements AND the comparison cell of the most significant bit and the comparison cells are connected to the inputs of the second element. OR whose output is connected

. with the second output of the node, the tens comparison nodes contain a high-order comparison cell consisting of two AND elements, nine comparison cells, each of which consists of four AND elements and an OR element, with the inputs of the first and. The second And elements are connected to the first input of the comparison cell, the first inputs of the third and fourth And elements are connected to the second input of the cell, the first input of the node is connected to the first input of the OR element, the output of which is connected to the second inputs of the second and fourth And elements and to the output of the comparison cell , the outputs of the first, second, third, and fourth elements of And are connected to the first, second, third, and fourth outputs of the reference cell, the second input of the elements

This OR is connected to the fourth entrance.

cells, elements OR, AND, the first information inputs of the corresponding bits are connected to the first inputs

comparison cells and the first element AND

⁵ high-order comparison cells, the second information inputs of the corresponding bits are connected to the second inputs of the comparison cells and to the first input

_{10 of the} second element And the high-order comparison cell, the third information inputs of the corresponding bits are connected to the second inputs of the And high-level comparison cell elements and to

5 to the third inputs of the comparison cells, the output of each] -th comparison cell, where 4 is 1.1.2,.,. 9 is connected to the fourth input (] + 1) of the reference cell, the outputs of the first element And the cell are equal to ₂₀ . Nia MSB and outputs first comparison cells are connected to the inputs of a first OR gate whose output is connected to the first ~ input of the first AND gate, a second input ₂₅ which Con chen vhodu'uzla to the first control, and the output - to the input of a second OR gate, the other inputs which is connected to the second outputs of the comparison cells, the output of the second element And the cell

₃₀ comparing MSB and third outputs of comparison cells are connected to the inputs of a third OR gate, whose output is connected to a first input of the second AND gate, the second input koto ₃₅ cerned connected to the second control input, and an output - to the input of a fourth OR gate, the other inputs of which are connected with the fourth outputs of the comparison cells, the outputs of the second and fourth

_4θ elements OR are connected to the first and second outputs of the node.

The block diagram of the device shown in the drawing,

The device contains blocks 1,2,3 issuance

₄₅ node 4 unit comparison, consisting of cell 5 comparison of the senior level, containing the elements of 6.7 And, nine identical cells 8 | , 8 ₂ ... 8 ₉ comparisons (of which only two are represented in the drawing) containing element 9 OR, elements 10, 11 AND and elements 12, 13 OR, P comparison nodes of dozens 14 142, ·. · 14 р ₇ . · Consisting

from element 15 And, cell 16 comparison

₅₅ senior order containing elements 17, 18 AND, elements 19, 20 OR and nine identical cells 21 _{1 (} 21 ^ ..,

21d comparisons (of which only three are shown in the drawing),

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containing elements 22, 23, 24, 25 AND and element 26 OR, elements 27 ·, 28, OR / element 29 AND, block 30 of the display, output tires 31, 32, 33.

The device works as follows ₅ times.

In the initial state, in the output unit 1, the code of the number of the lower tolerance value is entered, and in output unit 3, the code of the number of the upper tolerance value in accordance with the selected tolerances. In this case, the corresponding inputs of nodes 4 and 14, 14 2 .... 14 _n comparison

Signals from these blocks will be received by the logic level "1". In the process of measuring in 15 each decade of block 1, 2 of issuance of code 2 of the number of compared (controlled) parameter, the number increases (the device can work when entering the compared number into block 2 of issuance 20 immediately, similar to the numbers of tolerances in blocks 1, 3 of issuance). If the value of the most significant digit of the measured value is less than the established lower tolerance, then none of the elements 25

17, 22, 24 AND tens comparison node 14 will not coincide, therefore, the outputs of elements 27 and 28 OR will have logical "O" regardless of the comparison result in the previous 30 lower, bits (units). Similarly, the outputs of the elements 19, 20 OR signals will also be a logical "O". In this case, signals “O” are sent to both inputs of the display unit 30, with a “less” signal being output on the output bus 33.

If the numbers of values of the most significant digit of the measured value and the number of the lower tolerance are equal, ₄₀ logical signals of “1” will coincide only in one element 17, 22 And, for example, in element 22 And comparison cell 2C. The signal from this element 22 And, passing through the element 27 OR, will go to one ₄₅ of the inputs (first input) of the element 15 I. Now everything will depend on the values of the numbers of the previous low-order digit (units) of the measured value and the tolerance. If the measured value ( _5C ) (number) in the _low order is less than the tolerance, then in no element 6,

10 And node 4 of the low-order comparison will not match. In this case, at the output of the comparison node, the younger _{5 <} discharge from element 13 OR will be a signal of the level "0", which is transferred to the second hopper element 15 And the subsequent senior comparison node (tens). In that

element 15 And the match * does not occur, so the output of element 28 OR will be a logical "O", with the result that block 30 nvdikashshsh gives a signal "1" at the output 33 "less."

In case of equality of the numbers of the values of the measured value and the tolerance, the logical "Ι" will coincide in one of the elements 6, 10 And, for example in the element 10 And the comparison cell 8. At the same time on one of the 10 inputs of the element 13 OR there will be a signal "1", which through it is transmitted to the second input of the element 15 And the subsequent comparison node (tens). In element 15, a coincidence will occur and the signal level "1", passing through element 28 OR, will go to the first input of display unit 30, which outputs a signal "1" on output 32 "norm" '', provided that the compared number is less than the upper tolerance, i.e. the second input of the display unit 30 receives a logical "O".

If the measured value exceeds the tolerance in the high digit (dozens), a “1” coincides in one of the elements 24, 25 And, for example, in element 24 And the comparison cell 212 ι as in this discharge the code of the larger number of the measured value will go to the input previous cell comparison, for example, the input element 26 OR. The signal "1" of the compared number, having passed all the elements of 26 OR of the subsequent comparison cells, will go to the first input of all the subsequent elements 24,

25 And, as a result, there will be a coincidence of logical units in the element 24 AND cell 21 ^ comparison. The output signal from this element, passing through the element 28 OR, will go to the output of the high-order comparison node and, regardless of the comparison result in the previous lower comparison node (units), the device generates a signal at output 52 "normal", eats: the measured parameter is less than upper tolerance, or output 31 "more", if the measured parameter is greater than the value of the upper tolerance.

The signal "1" at the output 32 of the display unit 30 remains unchanged throughout the entire tolerance interval. If the measured value reaches the upper tolerance limit or exceeds it, then in the same way, at the output of the high-order comparison node from element 20 OR • a signal is output by the level "1". Wherein

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Both inputs of the display unit are signaled with a level of "1", as a result of which the last at output 31 outputs a signal "1" - "more".

In the proposed device in comparison 5. the well-known device significantly increased the speed of the device, since the codes of the compared numbers A, B and C are not set (set) on the switching elements, but supplied from the issuing blocks 10 lower and upper tolerances, for example, from memory blocks of digital computers, but directly from a digital measuring device, made on the fast-15 operating logic elements.

Claims (3)

Claim 1. A device for comparing numbers, containing blocks for issuing numbers, unit for comparing units, η units for comparing dozens, display unit, with outputs of the first, second and third units for dispensing connected to the first, second and third information inputs, respectively, of the unit for comparing units and tens comparison nodes, characterized in that, in order to increase speed, there the first and second outputs of the unit comparison node are connected to the first and second control inputs of the first comparison node of the tens, respectively, the first and second outputs of each a -th tens comparison node, where (~ 1,2, ..., {Π -1) are connected to the first and second _h controlling inputs of the g (l +1) -th tens comparison node, the outputs of the η-th comparison node are connected to the inputs of the display unit. 2. Device by π. 1, that is, that in it the unit of comparison of units contains two OR elements, a comparison cell of the most significant discharge, consisting of two AND elements and nine comparison cells, each of which consists of two AND elements , moreover, the first information inputs of the corresponding bits of the unit of comparison units connected with the first inputs of the elements AND cell comparison the senior discharge and comparison cells, the second information inputs of the corresponding bits of the node are connected to the first inputs of the second elements And the comparison cells of the senior bits and comparison cells, the third information inputs of the corresponding 20 25 thirty 35 40 45 50 55 the corresponding bits of the node are connected to the second inputs of the AND high-order comparison cells and to the first inputs of the OR elements of the comparison cells, the third high-level information input is connected to the second input of the OR element of the first comparison cell, the output of the OR element of each) -th, where) is 1, 2, ... 9 comparison cells are connected with the second input of the OR element () +1) —the comparison cells and with the second inputs of the AND elements of the comparison cell, the outputs of the first elements AND the comparison cell of the senior digit and the comparison cells are connected to the inputs of the first The first OR element whose output is connected to the first output of the node, the outputs of the AND elements of the comparison cell and the high-order comparison cells are connected to the inputs of the second OR element, the output of which is connected to the second output of the node. 3. Device by π. 1, which is based on the fact that there are dozens of comparison nodes containing a high-order comparison cell consisting of two AND elements, and nine comparison cells, each of which consists of four AND elements and an OR element, and the inputs of the first and The second elements And are connected to the first input of the comparison cell, the first inputs of the third and fourth elements And are connected to the second input of the cell, the first input of the node is connected to the first input of the OR element, the output of which is connected to the second inputs of the second and fourth And elements and to the output of the middle cell The outputs, the first, second, third and fourth elements of AND are connected to the first, second, third and fourth outputs of the comparison cell, the second input of the OR element is connected to the fourth input of the cell, the OR, AND elements, the first information inputs of the corresponding bits are connected to the first inputs of the cells. comparison and the first element And the high-order comparison cell, the second information inputs of the corresponding bits are connected to the second inputs of the comparison cells and to the first input of the second element And the high-order comparison cell , the third information inputs of the corresponding bits are connected to the second inputs of the elements AND the high-order comparison cells and to the third inputs of the comparison cells, each output _; | -th comparison cell, where} = 1,2 ,,, ^ 9 is connected to the fourth input () +1) -th 9 the comparison cells, the outputs of the first element AND the high-order comparison cells and the first outputs of the comparison cells are connected to the inputs of the first element, OR the output of which is connected to the first input of the first AND element, the second input of which is connected to the first control input of the node, and the output to the input the second element OR, the other inputs of which are connected to the second outputs of the comparison cells, the output of the second element AND the high-order comparison cells and the third outputs of the comparison cells are connected to the inputs of the third OR element, whose output is dinen with the first input of the second element And, the second input of which is connected to the second control input, and output 754409 ' ten to the input of the fourth element OR, the other inputs of which are connected to four • twisted outputs of the comparison cells, the outputs of the second and fourth elements ₅ OR connected to the first and second outputs of the node. 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