SU760089A1 - Binary number comparing device - Google Patents

Description

The invention relates to the field of automation and computing and can be used in the implementation of technical means of automation and digital computers to compare numbers represented by a serial code.

A device for comparing binary numbers, containing triggers, logic gates AND, OR-NOT and performing a comparison of modulo numbers represented by a sequential code, starting with the high-order bits (1), is known. This device for comparing numbers by module has a large amount of equipment and does not

¹ can compare binary numbers represented by a sequential code, starting at lower digits.

The closest technical solution to the proposed is a device containing a trigger with three stable states on the elements AND-NOT, the first and second inputs of which are connected to the outputs of the first and second elements AND-NOT, one of the inputs of which are connected to the output of the inequality element which is connected to the second inputs of the same elements AND-NOT, respectively, and

2

the outputs of the third and fourth elements AND-NOT, respectively, and one of the inputs of the third and fourth elements AND-NOT connected to the input bus device, and the other inputs to the output of the fifth element AND-NOT, the inputs of which are connected to the control bus and the corresponding trigger output (2).

The disadvantages of this device are its relative complexity and low speed.

The purpose of the invention is to increase the speed and simplify the device.

This goal is achieved by the fact that in a device for comparing binary numbers containing a three-stage trigger, AND-NOT elements, an unequal element, the first and second information inputs of the device are connected to the inputs of an unequal element, whose output is connected to the first inputs of the first and second AND elements -NO, the outputs of the first and second elements of the IS-NOT are connected to the first and second inputs of the three-stable trigger, the third input of which is connected to the first control bus, and the first output is

3 760089 4.

to the first input of the third NAND element, the second input of which is connected to the second control bus, the output of the third NAND element is connected to the second inputs of the first and second. elements NAND, and the third inputs of the first and second elements NAND are connected to the first and second information inputs of the device, respectively.

Functional diagram of the device shown in the drawing.

The device contains elements AND-NOT 1, 2, 3, elements AND-NOT 4, 5, 6, forming a three-stable trigger 7, element 8 unequalities, information inputs 9 and 10, tires 11 and 12 of the control, output tires 13, 14, 15 for the values A = B, A <B, and A> 'B, respectively, the output bus 16 is the sum of like bits of the numbers being compared.

The device works as follows.

The signal coming through the bus 12 * control low potential on the inputs of the elements YHE 4 and 6, the trigger 7 is set In the initial state - low potential at the output of the element AND NOT 5 and high potentials at the outputs of the elements AND NOT 4 and. 6. When comparing the numbers, ‘starting from the lower digits, a low potential is applied to the 1G control spike, which forms the output potential of the N-HE 3 element, regardless of the signal at the input connected to the output of the NAND 5 element, a high potential. This signal is fed to the inputs of the elements AND-NOT 1 and 2. Therefore, the signals at the outputs of the elements. NAND 1 and 2 depend on the signals at the information inputs 10, 9 and the signal at the ’exit of the unequal element 8. In case of equal digits of the compared numbers at inputs 9 and 10 at the output of the inequality element, in this case there is no signal and. The elements Y and N G and 2 do not work.

The absence of a signal at the output of the element 8 inequality and the output bus 16 means that the sum of the same-like digits of the compared numbers at the inputs 9 and 10 is equal to 0.

With different codes in the like digits, for example, "1" (low potential at information input 10) and "0" (high potential Η 3ι information input 9), at the output of element 8 of unequal values, in this case, a high potential appears. The appearance of the signal at the output of the inequality element and the output bus 16 means that the sum of the like digits of the compared numbers at information inputs 9 and 10 is 1. Due to the appearance of a high potential at the output of the non-equivalence element, the AND-NOT 2 is open in three

"inputs and the signal from its output goes to

the inputs of the elements are NOT 5, 6 and sets

on their outputs are high potentials that

The inputs of the element AND-NOT '4 are received. The remaining inputs also have high potentials (there is no “Reset” signal on bus 12 and the element IS-NOT 1 did not turn on), therefore, its output, forming a positive feedback circuit, has a low potential. Thus, the three-stable trigger 7 is established in the position at which, on the output bus 15, for the value A> B

A signal will appear (low potential).

When comparing the numbers represented by a sequential code, starting with the least significant digits, a single signal will appear at the output of the unequal element 8, the sum of the same digits of the compared numbers and the three-stable trigger 7 will switch as many times as the digits are not compared with each other (the state of this trigger will be determined last ( the most senior of the unmatched _2θ bits), so at the end of the comparison, its result will be correctly indicated by the outputs of the three-stable trigger 7.

On admission to the comparison of numbers, beginning with the high order bits that is determined you ₂₅ sokim potential bus control 11, operation of the apparatus is similar to the work by comparing the numbers LSB forward to the first incomparably, wherein in the output of the element 8 nonequivalence appears the unit ₃₀ ny sum signal homonymous bits of the compared numbers on the information inputs 9,

10 and a tri-stable trigger 7 will be switched, as a result of which a high potential is established at the output of the element NE-5.

This high potential arrives at the input of the element H – NO 3, at the output of which a low potential is formed, which flows at the inputs of the elements H – HH 1, 2 and does not allow them to be switched on. At the same time on; The outputs of the eleven ₄₀ cops of AND-NOT 1 and 2 will establish high potentials. Therefore, the three-stable trigger 7 will not switch until the end of the comparison, and its value, determined by the incomparable most significant bits of the numbers A and B, indicates

₄₅ correct result. *

, The appearance of a low potential at the output of the element AND-NOT 3 does not affect the operation of the element 8 of unequalities. Therefore, when comparing the numbers represented by a sequential code, starting with the upper digits, the output of the inequality element will receive a single signal of the sum of like digits of the compared numbers at information inputs 9 and 10 as many times as the digits did not compare with each other.

The proposed device 'allows you to compare binary numbers represented by a sequential code, starting' with both the lower and higher digits, and his work is not

five

depends on the time parameters of the elements' AND-NOT 4, 5, 6. In addition, the device for comparing binary Numbers performs summation of the same-named digits of the compared numbers, represented by a sequential code, starting from both the lower and the higher digits.

Such a construction of a device for comparing binary numbers distinguishes a device from a prototype by the number of used NAND elements, by speed and by the number of functions performed.

The device performs the functions of comparing and summing the same-digit bits of numbers represented by a sequential code, starting with both the lower and the higher digits.

Claims (1)

Claim A device for comparing binary numbers containing a three-stable trigger, elements of NAND, an element of inequality, the first 760089 6 and the second information inputs of the device are connected to the inputs of the unequal element, the output of which is connected to the first inputs of the first and second elements AND-NOT, the output of ₅ · dy the first and second elements AND-NOT connected to the first and second inputs of the three-stable trigger, the third input of which is connected to the first control bus, and the first output to the first input of the third element, 0 AND-NOT, the second input of which is connected to the second control bus, characterized in that, in order to improve performance and simplify the device, the output of the third lementa AND-NO element is connected to second vho15 rows of first and second AND-NO element and third inputs of first and second AND-NO elements are connected to first and second data inputs of the device, respectively.