SU1001482A1 - Counter - Google Patents

Description

(H) COUNTER

one

The invention relates to computing and automation and can be used for pulse counting.

A counter is known that contains, in each bit, the first and second memory triggers on AND-OR-NOT elements with corresponding links P

The closest to the proposed technical entity is a counter containing in each bit a binary ternary trigger and a switching trigger, with clock inputs of both triggers connected to the meter's input, the output of each bit being connected to the next bit input, and in each of the bits, the outputs of the binary-ternary trigger are connected to the corresponding inputs of the switching trigger, the outputs of which are connected to the corresponding information inputs of the binary-trigger trigger; l

A disadvantage of the known counters is low information capacity.

The purpose of the invention is to increase the information capacity of the counter.

Claims (2)

The goal is achieved. By the fact that the counter containing a binary triple trigger on the elements of IgILI-NOT, whose clock input is connected to the input of the given bit, and the input of the first bit connected to the input of the counter, is contained in each counter two triggers on the AND-OR-NOT elements, the direct output of the first of which is connected to the next-order input, and in each of the counter bits the inverse output of the second trigger is connected to the first information input of the binary-three-way trigger, with the second information inputs of which connected right and in ersny outputs respectively first and second flip-flops, the outputs of both straight triggers tre timi connected to data inputs of the binary-ternary trigger, wherein the first binary coded ternary output latch connected to the input ustanovn; 1 of the second trigger, with the reset input of which and the installation input of the first trigger are connected a second output of the binary trigger, the third output of which is connected to the reset inputs of their triggers, clock inputs of which are connected to the input of this bit. The drawing shows a diagram of the counter. The counter contains bits 1, each of which consists of a binary trigger on the AND-OR-NOT 2-4 elements, as well as the first and second triggers on the AND-OR-NOT elements 5, 6 and 7, 8 and the input 9 of this bit Each bit counter works as follows. Let the initial state at the outputs of the binary ternary trigger be set to 110. Then the first clock pulse sets the binary to three trigger to the state 011. After the nearest pause between the pulses applied to input 9, the trigger switches on elements 5 and 6, if both of these triggers on elements 5 6 and 7. 8 were in the zero logical state. The second clock pulse switches the binary-triple trigger to state 101, and in the pause after the second pulse, the trigger is reset on elements 5-6 and the trigger is set to 1 on elements 7 and 8. The third clock pulse is equivalent to the first clock pulse, and the fourth clock pulse the pulse returns the binary ternary trigger to the initial state 110. In the pause after the fourth pulse, the three heres on the elements 5i 6 and 7f 8 are set to the zero logic state. Thus, adding one AND-OR-NOT element to each of the bits of the counter allows to obtain an additional steady state of each of the bits, and therefore, the amount of information processed by each element increases by 10. Br. Keeping each of the bits two triggers that are included accordingly, significantly increases its information capacity. Claims of Invention A counter that contains in each bit a binary ternary trigger on an AND-OR-NOT element whose clock input is connected to the input of the given bit, and the first-time input is connected to the input of the counter, differing in that increase in information capacity, two triggers are introduced into each bit, on AND-OR-NOT elements: the direct output of the first of which is connected to the input of the subsequent discharge, and in each of the counter bits, the inverse output of the second trigger is connected to the first information input binary trinity about the trigger, with the second information inputs of which are connected the direct and inverse outputs of the respective second and first triggers, the direct outputs of both triggers are connected to the third information inputs of the binary three-way trigger, while the first output of the binary three-way Trigger is connected to the input of the second trigger, the reset input of which and the installation input of the first trigger are connected to the second output of the binary ternary trigger, the third output of which is connected to the reset inputs of both triggers, clock inputs of which connected to the input of this bit. Sources of information taken into account in the examination 1. The author's certificate of the USSR Vf, cl. And 03 K 23/02, 1977. 2. Mayorov S.А., Design of microelectronic digital devices. M., Soviet, 1977, p. 1b21bZ, rice. 5.11. "7 u shI