SU1160558A1 - Sequential counter - Google Patents

Description

The invention relates to automation and computing and can be used in the implementation of technical means in this area when building counters of large 5 digits.

Known serial counter on the elements AND-NOT, each discharge of which is constructed according to the scheme of "three triggers", containing an additional 10 elements for indicating the end points of transients, the output of which is connected to an external control automat, the output of which is connected to the counting input of the counter [1]. hell

The disadvantages of this counter are a relatively large amount of equipment and a relatively low speed.

The closest technical solution to the proposed is a sequential counter containing in each digit the main and auxiliary triggers, each of which contains the first and second elements AND-OR-NOT, basically the output of the first element I-IPI-NOT connected to the first inputs of the first and second groups of inputs on the AND of the second element Y-OR-NOT and is the inverse ad output of the main trigger, the direct output of which is the output of the second element AND-AND-NO of this trigger, which is connected to the first inputs of the first and second oh groups of inputs on the first element AND-OR-NOT, the second inputs of the first groups of inputs on AND

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the first and second elements AND-OR — NOT are the clock input of the main trigger, the reset inputs and settings of which are the second inputs of the second input groups of AND, respectively, of the first second AND-AND-NOT elements of this trigger, the first inputs of the first groups of inputs of AND first and the second elements AND-OR-NOT auxiliary trigger are connected and are the clock input of this trigger, the reset and installation inputs of which are the second inputs of the first input groups of AND, respectively, the first and second elements AND-OR-NOT of this trigger, inv The rsny and direct outputs of which are connected to the outputs of the second and first elements X-OR-NOT, respectively, which are combined with the inputs of additional groups of inputs of AND, respectively, the first and second elements AND-OR-NO, the clock inputs of the main and auxiliary trigger in each of the bits are combined and connected with an inverse ^- the output of the auxiliary flip-flop of the previous different number in all digits other than the first, in which the clock inputs of the main and auxiliary triggers are sequentially counting input of the counter, The direct th output vspo · mogatelnogo trigger is connected to the reset input of the flip-flop of the same main discharge, the main trigger direct output connected to the reset input of the auxiliary flip-flop, the same discharge entrance Fitting vspomogatel3 · 1160558

the trigger of which is connected to the inverse output of the main trigger, the inverse output of the auxiliary trigger of the last discharge is connected to the installation input of the main trigger of the same discharge, and the inverse output of the main trigger and the direct output of the auxiliary trigger of the first discharge are connected to the inputs of the first group of inputs And element 10

AND-OR-NOT, the output of which is the output of the ready signal of the sequential counter I.

A disadvantage of the known sequential counter is the relatively low reliability with bit depths that exceed the maximum possible OR combination coefficient by OR.

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. The purpose of the invention is to increase the reliability of the counters having a bit width exceeding the maximum allowable combination ratio of OR.

The goal is achieved

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the fact that in a sequential counter, with the number of digits exceeding the maximum allowable combination ratio for the inputs of the OR elements, contains in each digit the main and auxiliary triggers, each ^ 0 of which contains the first and second elements AND-ILY-NOT, basically the trigger output The first element AND-OR-NOT is connected to the first inputs of the first and second groups of inputs by AND the second '35

element AND-OR-NOT and is the inverse output of the main trigger, the direct output of which is the output of the second element AND-OR-NOT of this trigger, which is connected to the first 40 inputs of the first and second groups of inputs on the first element AND-OR-NOT, the second the inputs of the first groups of inputs for AND of the first and second elements of AND-ILY-NOT are the clock input of the main 45 trigger, the reset and input inputs of which are the second inputs of the second groups of inputs of AND for the first and second elements AND-OR · of this trigger, the first first 50 g outlets And SCP inputs of first and second AND-OR-NO element are connected and the auxiliary trigger is a clock input of the flip-flop, a reset input 55 and whose settings are the second inputs of first AND input groups of first and second AND-OR-NO element of this

trigger, inverse and direct output of which are connected to the outputs of the second and first elements X-OR-NOT, respectively, which are combined with the inputs of additional groups of inputs on AND, respectively, of the first and second elements I-IPI-NOT, the clock inputs of the main and auxiliary triggers in each of bits combined and connected to the inverse output of the auxiliary trigger of the previous discharge in all bits, except the first, in which the clock inputs of the main and auxiliary triggers are the counting input of the serial chetchika,

I

the direct output of the auxiliary trigger is connected to the reset input of the main trigger of the same discharge, the direct output of the main trigger is connected to the reset input of the auxiliary trigger of the same discharge, the installation input of the auxiliary trigger is connected to the inverted output of the main trigger of the last discharge of the auxiliary trigger of the last discharge connected to the installation input the main trigger of the same discharge, and the inverse output of the main trigger and the direct output of the auxiliary trigger of the first discharge are connected to the input E first. a group of inputs for the AND element. AND-OR-NOT., the output of which is the output of the ready signal of a sequential counter, in each digit, except the first, an element H-OR, the inputs of the first group of inputs by AND co

This is connected to the inverse output of the main and direct output of the auxiliary trigger of this discharge, the direct output of the main trigger of which is connected to the first input of the second group of inputs AND of the AND-OR element of this discharge, the second input of which is combined with the installation input of the main trigger of this discharge and connected all digits, except the last, with the output of the X – OR element of the next digit, and the output of the X – OR element of the second digit is connected to the input of the main trigger setup of the first digit and the first input of the second input group s on and the AND-OR-NO, the second input

which is connected to the direct output of the main trigger of the first discharge.

five

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The drawing shows a structural diagram of a sequential counter.

A sequential counter contains bits 1-3, in each of which there is a main 4 and auxiliary 5 triggers, each of which contains the first 6 and second 7 elements AND-OR-HE ^ in the main trigger 4 output-the first element AND-ILY-NOT 6 is connected to the first inputs of the first and second groups of inputs on AND the second element Y-OR-NOT 7 and is the inverse output 8 of the main trigger 4, the direct output 9 of which is the output of the second element J-OR-NOT 7 of this trigger, which is connected to the first inputs of the first and second groups of inputs on the first element of the I-YL - NOT 6, the second inputs of the first groups of inputs of AND 6 of the first 6 and second 7 elements AND-YLI-NE · are the clock inputs 10 of the main trigger 4, the reset inputs ί1 and installation 12 of which are the second inputs of the second GROUPS of the inputs AND respectively, the first 6 and second 7 elements AND-YLI-NOT of this trigger, the first inputs of the first groups of inputs on Ipervy 6 and the second 7 elements AND-OR-NOT auxiliary trigger

5 are connected and are the clock input 13 of this trigger, the reset inputs 14 and the settings 15 of which are the second inputs of the first groups of inputs of AND 6, respectively, of the first 6 and second 7 elements of the I-YLI-NOT of this trigger, inverse 16 and the direct 17 outputs of which are connected to the outputs respectively the second 7 and the first 6 elements AND-OR-NOT, which are combined with the inputs of additional groups of inputs on AND respectively the first.

6 and the second 7 elements are AND-OR-NOT, the clock inputs 10 and 13 of the main 4 and auxiliary 5 flip-flops in each of the digits are combined and connected to the inverse output 16 of the auxiliary flip-flop 5 of the previous discharge in all digits, except the first one, in which the clock inputs 10 and 13 main 4 and auxiliary 5 flip-flops are the counting input 18 of a sequential counter, the direct output 17 of the auxiliary trigger 5 is connected to the reset input 11 of the main trigger 4 of the same discharge, the direct output 9 of the main trigger 4 is connected to the reset input 14 , the trigger trigger 5 of the same discharge input 15 of the installation of the auxiliary trigger 5 of which is connected to the inverse output 8 of the main trigger 4, the inverse output 16 of the auxiliary trigger 5 of the last discharge is connected to the input 12 of the installation of the main trigger 4 of the same discharge, and the inverse output 8 of the main trigger 4 and direct output 17 of the auxiliary trigger 5 of the first discharge 1 is connected to the inputs of the first group of inputs of AND AND-YLI-NOT 19, the output of which is the output 20 of the ready signal 15 of a sequential counter. Each digit, except the first one, also contains an AND-OR element 21, the inputs of the first group of inputs of AND of which are connected to the inverse output 8 20 of the main 4 and direct output 17 of the auxiliary 5 flip-flop, this discharge direct output 9 of the main flip-flop 4 of which is connected to the first input the second group of inputs is 25 AND of the I-ILY 21 element of this discharge, the second input of which is combined with the input 12 of the main trigger 4 installation of this discharge and is connected in all the bits except the POS, the output of the AND-OR element 21 of the next discharge Elegance AND-OR 21 of the second discharge is connected to the input 12 of the installation of the main trigger 4 of the first discharge and the first input of the second group of inputs AND AND-OR-HE 19, the second input of which is connected to the direct output 9 of the main trigger 4 of the first discharge 1.

⁴⁰ Serial counter operates as follows.

Consideration of the counter will start with the last digit 3. When applying values to its counting input

⁴³ single logical signal occurs with the inversion of information from the main trigger 4 bits 3 13 its auxiliary trigger 5. This process ends with

5® on the direct output 17 of the auxiliary trigger 5 a single value of the logic signal is established, provided that the same value is available on the inverse output 8 of the main

⁵⁵ flip-flop 4, and as a result, a single logic signal will appear at the output of the element 21 of discharge 3. When applying to the counting input 22 bit 3

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of the signal of logical zero, the information from the auxiliary trigger 5 of this bit is copied to its main trigger 4. This process ends with a zero logic signal on the direct output of the main trigger 4, provided that the same value exists on the direct output 17 of the auxiliary trigger 5 and as a result, at the output of the element 22 of this category, a zero logic signal will appear.

Thus, the appearance of a zero or a single logical 15

the signal at the output of the element 21 of discharge 3 indicates the completion of transients in this discharge, caused by applying to the counting input of the same value. 20

Digit 2 works similarly to that considered, but when as a result of applying the value of a logical unit signal to the 22-bit counting input 22, zero is recorded at 25. Auxiliary trigger 5 and a single logic signal will appear at the inverse output 16 of this trigger, the same value will appear at the element output 21 bit 2 only β ₀ after the switch 3 ends the switch and the value of a single logical signal also appears at the output of the last element 21. If, as a result of supplying a single logical signal to a 22-digit 2 counting input, a unit is recorded in its auxiliary trigger 5, then the value of a single logical signal at the output of element 21 of this discharge will appear at the end of the recording, regardless of discharge operation 3. However, in the next phase of discharge operation 2, when a zero-point-zero signal is applied to its counting input 22, the unit will be written to the main trigger 4 of this discharge only after the switching of discharge 3, caused by the feed to the counting, is completed. the input 22 of the last zero logic signal from the inverted output 16 of the auxiliary trigger 5, bit 2, and the output of the element 21, bit 3 will receive the value of the zero logic signal. Only after this, after the unit has been written to the main trigger 4 of discharge 2 at the output, the element 21 of this discharge will receive a zero logic signal.

Thus, the appearance of a zero or a single logical signal at the output of the element 21 of discharge 2 indicates the completion of transients in this discharge, caused by applying to its counting input 22 of the same value.

In this case, the transients in discharge 3 are either also completed or are in such a stage that changing the value at the counting input 22 of discharge 2 will not prevent their proper termination, as a result of which the next phase of discharge 2 will also be completed.

Digit 1 works similarly to the previous one with the only difference that after the end of its switch, caused by the feeding of the next value to the counting input 18 of discharge 1 (i.e., the counting input of the counter), the output of the element 19 is set to the opposite value. This value from the output of the element 19 is fed to the input of the external control automaton 23, which causes the following change in the value at its output, and consequently, at the counting input 18 of the counter.

Thus, each change in the value at the counting input of the counter occurs only after the transient processes in the discharge 1, as well. transients in _β bits 2 and 3 either complete either or will be at such a stage that this change will not prevent their proper termination, the result of which will allow the first digit 1 to switch in the next phases of the counter, which guarantees the correct functioning of the proposed counter on the magnitude of the delays of its elements and their ratios.

For the implementation of the proposed counter, regardless of the number of its digits, only the elements 2I-2, OR-NOT are used, i.e. elements with the minimum number of inputs.

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Claims (1)

SEQUENTIAL COUNTER with the number of digits exceeding the maximum allowable combination ratio for the inputs of the elements OR, containing in each digit of the main and auxiliary triggers, each of which contains the first and second AND-OR-NOT elements, basically the trigger output of the first AND-OR-NOT element is connected to the first inputs of the first and second groups of inputs through AND of the second AND-OR-NOT element and is inverse the output of the main trigger, the direct output of which is the output of the second AND-OR-NOT element of this trigger, which is connected to the first inputs of the first and second groups, the AND inputs of the first AND-OR element, the second inputs of the first input groups of the first and the second element of i-iline are clock main trigger input, a reset input and whose settings are the second inputs of second AND input groups of first and second elements Q-NOR this trigger, per- ⁴ stems inputs of first AND input groups of The first and second elements of the AND-OR-NOT auxiliary trigger are connected * and are the clock input of this trigger, the reset and installation inputs of which are the second inputs of the first groups of inputs of AND respectively the first second element AND-OR-NOT of this trigger, inverse and direct outputs which are connected to the outputs of the second and first elements AND-OR-NOT, respectively, which are combined with the inputs of additional groups of inputs on AND, respectively, the first and second elements AND-OR-NOT ₍ clock inputs of the main and auxiliary trig geers in each of the digits are combined and connected to the inverse output of the auxiliary trigger of the previous discharge in all bits, except the first one, in which the clock inputs of the main and ° auxiliary triggers are the counting input of a serial counter, the direct output of the auxiliary trigger of the same the discharge, the direct output of the main trigger is connected to the reset input of the auxiliary trigger of the same discharge, the installation of the auxiliary trigger of which is connected to the inverse th output of the main trigger inverted output of the last flip-flop of the auxiliary discharge is connected to the input for setting the main trigger the discharge of the same, and an inverse output of the main trigger and direct access to the auxiliary trigger discharge of the first connected to inputs of first AND input group of AND element. 1 160558 AND-OR-NO element whose output is the output ready signal sequence Tel'nykh counter ^1, characterized in that, in order to increase reliability, in each stage, except the first, introduced YLI-AND gate, the inputs of first AND input group are connected to the inverse output of the main and direct output of the auxiliary trigger of this discharge, the direct output of the main trigger of which is connected to the first input of the second group of inputs of AND AND-OR element of this discharge, the second input of which is combined with the installation input of the main trigger of this discharge and is connected in all the discharges except the last with the output of the AND-OR element of the next discharge, and the output of the J-OR element of the second discharge is connected to the installation input of the main trigger of the first discharge and the first input of the second group of inputs on the AND-OR-NOT element, the second input of which is connected to the direct output of the main trigger of the first discharge. one