SU1661774A1 - Memory units addressing device - Google Patents

Abstract

The invention relates to computing and can be used to address memory blocks. The aim of the invention is to simplify the device and expand its functionality by implementing the mode of accessing the memory blocks in both increasing and decreasing order of formation of the overflow feature. The device contains an address register 1, a decoder 2, a group of N switches 3, a group of N first switching elements 4, a group N of second switching elements 5, an encoder 7, a group of N elements AND-OR 9, an additional switch 10, an additional switching element 11 of the second type and additional element AND-OR 12. 1 Il.

Description

one

(21) 4678634/24

(22) 04/14/89

(46) 07.07.91. Bksh. Number 25

(72) O.A.Titov and O.Yu.Gordienko

(53) 681.325 (088.8)

(56) USSR Author's Certificate No. 1388877, cl. G 06 F 12/00, 1986.

USSR Author's Certificate No. 1573458, 01/30/89.

(54) DEVICE FOR ADDRESSING MEMORY BLOCKS

(57) The invention relates to computing and can be used to address memory blocks. The aim of the invention is to simplify

devices and expansion of functionality due to the implementation of the addressing mode to the memory blocks both in ascending and descending addresses of the formation of an overflow sign. The device contains the address register 1, the decoder 2, the group n of switches 3, the group n of switching elements 4 of the first type, the group n of switching elements 5 of the second type, the encoder 7, the group of elements AND-OR 9, the additional switch 10, the additional switching element 11 of the second type and additional element AND-OR 12. 1 Il.

The invention relates to computing and can be used to address memory blocks.

The purpose of the invention is to simplify the device and expand its functionality by implementing the access mode to the memory blocks in both increasing and decreasing addresses and creating a sign of overflow.

The drawing shows a functional diagram of the device for addressing memory blocks.

The device contains a register 1 adress Oa, a decoder 2, a group n of switches 3, a group n of the first switching elements 4 (EC1), a group of the Switching elements 5 of the second type (EKI), an address input 6, an encoder 7, 4 address output 8, the group n of the elements AND-OR 9, the additional switch 10, the additional switching element 11 of the second type, the additional element AND-OR 12, the input 13 is controlled and the output 14 overflow.

The AND-OR element implements the logic function F A + B-C, where A, B, C is the lo- cal state of the signals at the 1st, 3rd inputs, respectively. (EC of the 1st type implements the following logic functions: at the first output, at the second output K, where H, K - logical state at the first and second inputs, respectively.

The switching element of the 11th type is a multiplexer connecting the signal from the control input to the output of signals from either the first or the second inputs.

The device works as follows.

The switches 3 are set to the states corresponding to the states of the memory blocks. The high level signal (WU) at the output of the switches corresponds to the block on (Goden) state, the low level signal (CI) - the Block is off (not cold).

Consider the operation of the device in the mode of accessing memory blocks by growing addresses.

According to the address, which is stored in address register 1, at the i-th output of the decoder 2, a signal is generated by the slave, which activates the selected i-th AND-OR element, the output of which is set by the slave.

If a VU is installed at the output of the 1st element AND-OR, and the next (1 + 1) -th switch is on, then the output of the next (i + 1) -ro EC II, second input and second EC output I is formed by the RC, and at the first exit. to (i + O-ro EK1 OU, specifying the OU and at the output of the next (i + 1) -th element AND-OR.

Thus, at the second output of the next (i + 1) -ro ECI I, a VU of the address signal of the next working memory block is generated, which is then encoded in the encoder 7 and in the binary code arrives at the output of the device. At the same time, on all other inputs of the encoder 7, the second outputs of EC I is installed by a device. If the decoder 2 activates the last n-th output, the output of the n-th element AND-OR, the device overflow output 14 is formed by a VU, and the WU signal is simultaneously fed to the first input of the additional EC II, and also to the overflow output 14 and the second input of the additional element AND-OR. If the additional and first switches are turned on, the second output of the first EC I is formed by a slave, which then enters the encoder.

If the (i + 1) -e switches that follow the selected i-th output of the decoder 2 are turned off, then the output of one of the ECI I corresponding to one of the following enabled memory blocks is set by the slave.

If the last switch is turned off, then at the second output of EC I, a WU is formed, and at the output of the nth element AND-OR, an additional EC II, the output 14 of the device is overflow - WU, which indicates the device is overflow. In this case, if the additional and first switches are turned on, the output of the additional element AND-OR and the second output of the first EC I is set up by the VU, the 1st input of the encoder 7 is accessed.

The work of the proposed addressing device in the mode of accessing the memory blocks in descending order of addresses occurs in the same way as in addressing ascending addresses, except for the order of switching between the AND-OR and EC elements of the I- and 11th types among themselves, which implemented by

to the previously described algorithm based on the control signal of increasing and decreasing I addresses, arriving at the control inputs of EC II.

In the mode of accessing the memory blocks by descending addresses at the address contained in address register 1, the proposed device generates the address of the next enabled memory block with a smaller address. With the zero output of the decoder 2 selected, at the output of the additional element AND-OR 12, the second input of the n-th EC I, the second input of the n-th element AND-OR 9 is set by a VU.

If the nth switch is on, then the output of the nth element, AND-OR 9, is formed by the NU, and at the second output of the nth ECI and at the nth input of the slave encoder. Thus, the addressing to the next operable block of memory (n-th) occurs.

Thus, the i-th address of the address in the proposed device always corresponds to the i-th memory block from among the disconnected and unused memory blocks. The proposed device implements the modes of accessing the memory blocks both in ascending and descending addresses and forms a sign of overflow.

Claims (1)

Invention Formula 7 A device for addressing memory blocks containing an address register, a decoder, a group of switches, a group of switching elements of the first type, a group of switching elements of the second type, an address coder, the information input of the address register being the address input of the device, the output of the address register being the decoder input, the output of the first switch is connected to the first input of the first switching element in the group ten 15 20 25 thirty 35 Qd5 type, the output of the encoder is the address output of the device, characterized in that, in order to simplify the device and expand its functionality by implementing the mode of accessing the memory blocks both in ascending and descending addresses and forming when-: overflow sign, an additional Switch, an additional switching element of the second type and a group of AND-OR elements are entered into it, the decoder zero output connected to the first input of the additional AND-OR element, and the i-th decoder output (where,. .., p) is connected to the first input of the 1st element AND-OR, the second input of which is the output of the 1st switching element of the second type, and the third input of the 1st element AND-OR is connected to the first output of the 1st switching element the first type, the third input of the additional element AND-OR is connected to the output of the additional switch, the output of the 1st element AND-OR is connected to the first input (i + 1) -ro of the switching element of the second type, as well as to the second input (irl) -ro switching element of the second type, the output of the 1st switch is the first input of the 1st switching element of the first type, the second input of which is connected to the output of the 1st switching element of the second type, the output of the additional switch is the third input of the first AND-OR element, the second output of the 1st switching element, the first type is the i-th input of the encoder, the third input The 1st element com-i mutation of the second type is the control input of the device, the output of the additional switching element of the second type is connected to the second input of the additional AND-OR element and is the output of the sign of the device overflow.