SU1573458A2 - Addressing device - Google Patents

Abstract

The invention relates to automation and computing and can be used as a module for hardware mutual transformation of logical and physical addresses of any functionally complete blocks (processors, memory blocks, etc.). The aim of the invention is to extend the functionality of the device and its application area by reversing the physical address of the block into its logical address. The device contains a group of switches 1-3 logical address, register 4 logical address, the decoder 5 logical address, the first group of elements 6 and 7 OR, blocks 8 and 9 switching of the first, second group, the encoder 11 physical address, register 13 physical address, the decoder 14 the physical address, the second group of elements 15 and 16 OR, the encoder 17 logical address. The introduction of the register 13, the decoder 14, the encoders 11, 17, and the change in the design of the switching units allows for the conversion of a logical address to a physical address and vice versa, with direct and inverse transformations can occur simultaneously and independently of each other. 3 il.

Description

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is an extension of the functional capabilities of the device and its area of application due to the inverse transformation of the physical address of the block into this logical address. The device contains a group of switches 1-3 of the logical address, a logical address register 4, a logical address decoder 5, the first group of elements OR 6 and 7, the first and second switching units 8 and 9, the physical address encoder 11, the physical address register 13 to computer equipment automation j, can be used as a module for {hardware mutual transformation of the Logical and physical addresses of any functionally complete blocks (processors, memory blocks, etc.) and is improved device on auth. St. No. 1388877.

The aim of the invention is to expand the functionality and the field of application of the device by reversing the physical address of the block into its logical address,

Figure 1 shows the functional diagram of the device for the three blocks in figure 2 and 3 - functional diagrams of the switching elements of the first and second groups, respectively.

The device contains a group of switches, switches 1-3, the register 4 of the logical address, the decoder 5 of the logical address, the first group of elements OR 6 and 7, blocks 8 and 9 of the switching of the first and second groups, the input 10 of the logical address of the device, the encoder 11 of the physical address, output 12 of the physical address of the device, register 13 of the physical address and the decoder 14 of the physical address of the device, the second group of elements OR 15 and 16, the encoder 17, the output 18 of the logical address of the device, input 19.

The device works as follows.

Switching unit 8 (FIG. 2) implements logical functions,,, where G, H, 0, K, L, P are signals on the first, second, third inputs and outputs of switching unit 8 of the first group, respectively.

rez, the decoder 14 of the physical address s the second group of elements OR 15 and 16, the encoder 17 of the logical address. The introduction of the register 13, the decoder 14, the encoders 11, 17, and the change in the design of the switching units allows for the conversion of a logical address to a physical address and vice versa, with direct and inverse transformations can occur simultaneously and independently of each other. 3 il.

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Switching unit 9 (FIG. 3) implements the functions,, and, where A, C, B, M, D, E, F, N are signals on the first - fourth inputs and first - fourth outputs of the switching unit 9 of the second group, respectively

Immediately after the power is supplied, the switching session begins in the matrix of blocks 8 (9) in accordance with the switch signals - 1-3. A high level signal (TL) at the output of switches 1-3 corresponds to the state of the block on / healthy, a low level signal (LL) - to the state of the unit turned off / faulty.

After completion of transient processes in the matrix of switching blocks 8 (9), the device is ready for operation in the interconversion mode of logical and physical addresses. In this case, the logical address j is always associated with such a physical address i, which corresponds to the j-th functional block from among the disconnected / healthy blocks and vice versa (i.e. the correspondence between the fields of logical and physical addresses for a given distribution of validity flags given by the switches 1-3, are one-to-one).

For example, suppose that switch 1 is in the position of NU, and switches 2 and 3 are in the –BU position. Then logical address 1 at output 10 corresponds to physical address 2 at output 12, and physical address 3 at input 19 corresponds to logical address 2 at output 18. Moreover, the conversion of logical addresses to physical addresses and vice versa occurs completely independently of each other,

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which allows, without interrupting a call to a serviceable block (when converting a logical address into a physical address), to find out, for example, which logical address corresponds to information in a memory block with a specific physical address.

Claims (1)

Invention Formula Device for addressing auth. St. No. 1388877, characterized in that, in order to expand the functionality and application area of the device by converting the physical address of the block to its logical address, a physical address encoder, physical address register, physical address decoder, second element group OR, encoder are entered into it. the logical address, where the information input of the physical address register is an input of the physical address of the device, the output of the physical address register is connected to the input of the decoder n ten 15 20 the physical address, the jth output of the physical address decoder is connected to the third inputs of the switching units of the first group and the fourth inputs of the switching units of the second group of the jth row of the matrix, the third outputs of the switching units of the first group and the fourth outputs of the switching units of the second group of each column of the matrix, except the last , are connected to the inputs of the corresponding OR elements of the second group, the outputs of the OR elements of the second group and the third output of the switching unit of the first group of the last column of the matrix are connected with the corresponding odes logical address encoder, whose output is the output of logical device addresses, OR element outputs the first group and the first output block of the first group of switching matrices of the first column are connected to respective inputs of an encoder of the physical address, which is output 25. The output physical device addresses. B FIG. one M about & I TS.J FIG. H AT D from F