SU1619257A1 - Device for computing sum of products - Google Patents

Abstract

The invention relates to computing and can be used in specialized devices for digital inLormation processing. The aim of the invention is to improve the accuracy of calculations. The device contains a data register 1, a data bus 2, an address register 3, an address bus 4, a control block 5, a control bus 6, a query bus 7, a register group 8 9, a register group 10 11, an intermediate calculation block group 12, a multi-input adder 14, register 15 results, output 16. 1 e.p., f-ly, 3 silt, 2 tab. (L

Description

the dinenees with the first outputs of the switch output blocks of the switches are connected to the outputs of intermediate computing, the control inputs of the blocks of intermediate computing are connected to the second output of the control unit, each block of intermediate

corresponding inversion nodes and with the second inputs of the corresponding comparison cx, the outputs of the first and second comparison circuits are connected to the control

 switches connected to the outputs

corresponding inversion nodes and with the second inputs of the respective comparison circuits, the outputs of the first and second comparison circuits are connected to the control

calculation contains the register, the adder, the inputs of the corresponding switch of the Four switch, the first and second elements of OR and the element of the ban, the first information inputs of the first and second switches are connected to the corresponding information inputs of the block, which, in order to improve the accuracy of calculations , it contains data registers and addresses and two groups of registers, and each intermediate calculation block contains two more inversion nodes, three comparison circuits, three AND elements, a third OR element, two e element NOT and element for 0

five

The ditch, the outputs of which are connected to the inputs of the third comparison circuit, the output of the first comparison circuit is connected to the first inputs of the first, second and third elements And, the output of the second comparison circuit is connected to the input of the first element NOT and to the second inputs of the second and third elements And, the output of the third circuit the comparison is connected to the second input of the first and the third inputs of the second and third elements And, while the inputs of the first element And the first and second inputs of the second element And the second input of the third element And

are inverse, the output of the first element AND is connected to the first inputs of the first and second elements OR, the output of the first element PE is connected to the second input of the second element OR and to the input of the second element NOT, the outputs of the second and third elements AND are connected to the corresponding inputs of the first element

element OR, the output of which is connected by jQ is not with the output of the trigger, and the output is with

with the first control input of the third switch, the second control input of which is connected to the output of the third comparison circuit, the output of the second

the OR element is connected to the first control j to the second output of the block and to

the fourth control input, the second control input of which is connected to the output of the second element, the first, second, third and fourth information inputs of the third and fourth switches, are connected in pairs to the inputs and outputs of the first and second inversion nodes, the output of the third switch is connected to the information input of the register and the first input of the prohibition element, the second input of which is connected to the output of the delay element, and the output to the first output of the intermediate computing unit, the third output of which is connected to the output the register whose shift input is connected to the input of the delay element and to the input of the block, the output of the fourth commutator

dinene with the first input of the adder, the second input of which is connected to the input of the device constant, and the output - to the second output of the block.

Claims (2)

1 -v; “Ј -и; 6U, - v; and; 925710 2. The device according to claim 1, wherein the control unit comprises a pulse generator, an element I, a counter, three decoders, four elements No. 11, a delay element and a trigger, the output of the pulse generator connected to the first input of the element And, the second input of which is connected by the counter input, the output of which is connected to the input of the first decoder, the first output of which is connected to the sixth output of the block, and the first input of the OR element, the output of which is connected to the first output of the block, whose input is connected to the inputs of the second and third decoders, the first and last outputs of which are connected to the trigger inputs, the remaining outputs of the second decoder are connected to the fourth output of the block and to the inputs of the second element OR, the remaining outputs of the third decoder are connected to the fifth output of the block and to the inputs of the third element OR, the outputs of the second and third elements OR are connected to the inputs of the fourth OR element, whose output is connected to the third output of the block, and to the input of the delay element, you the stroke of which is connected to the sixth output of the block, the last output of the third decoder is connected to a nulling counter input. Table 1 Fyu.g Table 2 Fig.Z