SU1149246A1 - Device for counting number of ones - Google Patents

Abstract

A device for counting the number of units that contains input and output registers, converters of binary code in the code of the number of units, summing nodes, each of which contains a combinational adder, and the inputs of the converters of binary code in the code of the number of units are connected to the outputs of the corresponding groups of bits of the input register, different by the fact that, in order to expand the functionality by organizing the counting of the number of units in different groups of a given length, each Two switches are provided, with 1 first and second input groups of the i-ro combinational adder of the first rus summing node connected to the outputs

Description

The invention relates to a computational technique and is intended to count the number of units in daoic numbers. The aim of the invention is to expand the functionality by organizing the counting of the number of units in different groups of a given length. FIG. 1 shows a block diagram of a device for counting the number of units in FIG. .2 - structure on the summing node scheme. The device for counting the number of units contains an input register 1, converters 2 binary code into the code of the number of units, summing nodes 3.t-3.L, output register 4, control inputs 5.1 5 .L. The day of the 1st node includes the combination switchboard 6, the first switch 7, the second switch 8, the input 9 of the first term, the input 10 of the second term, and the outputs 11 and 12 of the summing node. The device works as follows. A binary number is placed on the input register 1 (Fig. 1), in which (or in the given groups of which) the number of units is required to be counted. From the outputs of input register 1, information is fed to the inputs of converters 2 of binary code to the code of the number of units, from the outputs of which the received codes of the number of units of input to the summing nodes 3.1 of the first rus. The result obtained at the output of 12 cy and the junction node 3.1 of the 1st Russ is one of the summands for the summing node 3 (+1) Who is the Russ, where K is 2, ..., logj m. When requiring the formation of the resulting sums of units in groups of a given size only in the lower bits of similar groups of bits to the output register 4, the minimum size of the group is determined by the extrusion n, „; N, where n ,, n is the minimum size of the group, and N is the size of the input register 1, the groups in which the number of units is simultaneously calculated must be equal to the magnitude of a multiple of two. The number of converters of 2 binary code to 6 code of the number of units is chosen N equal to m. The width of each summing node of the 3.fth rus is determined as + J2og2. and their number as N / n 2 W / 2 ,, Summing node 3. With number j (Fig. 2), on inputs 9 and 10, information from outputs 12 of summing nodes 3 (1-1) or from outputs of converters 2 is binary code in the code of the number of units for 1 with numbers (2j - 1) and 2j, respectively. Information from input 9 is fed to the first group of information inputs of the first switch 7, having a width equal to the width of summing node 3., and the first group of inputs of the combinational adder 6. Information from input 10 is fed to the first group of information inputs of the second switch 8 and to the second a group of inputs of the combinational adder 6. The sum, formed at the outputs of the combinational adder 6, goes to the second group of information inputs of the second switch 8. Thus, at a resolving potential of 1 for control The input terminal 5.C connects to the outputs 11 and 12 of the summing node, respectively, the second inputs of the first and second switches 7 and 8. To obtain at output 11, which is connected to the corresponding bits of the output register 4, zero information is given at 1R1 (potential on the control An input 5.P. The second group of information inputs is connected to the bus value O of the device. If there is no resolving potential at the control input 5.P, the outputs from the node 11 and 12 receive information from the inputs of the first and second components but. Dp formation in the output register 4 sums of units in groups of 2 bits (a O, 1, ... log 2 and) is necessary for all Russ for which fi a, apply the resolving potential to their control inputs 5..

In the proposed unit counting device, dynamic reorganization is provided for simultaneous processing of groups of bits of various reconfigurable counting devices. High degree

S.1

11492464

; The regularity of summing nodes 3.1-3.2 allows the use of large-scale microelectronic circuits for the implementation of such devices, which ensures a small amount of the device.

5.L

Fi, 1

12

i (i-n

//

r

12

dri

72

at

FIG. 2

Claims (1)

DEVICE FOR CALCULATING THE NUMBER OF UNITS, containing input and output registers, binary code converters to the number of units code, summing nodes, each of which contains a combinational adder, the inputs of the binary code converters to the number of units code connected to the outputs of the corresponding groups of bits of the input register, characterized in that, in order to expand functionality by organizing the calculation of the number of units in various groups of a given length, d are introduced into each summing node and the switch, and the first and second groups of inputs of the combinatory adder i-ro of the summing node of the first tier are connected to the outputs (2i-1} -ro and the 21st binary code converters to the number of units code, respectively (i = 1, ..., m / 2 ^ m is the number of bit groups of the input register), in each summing node, the first and second groups of information inputs of the first switch are connected to the first group of inputs of the combinational adder and the value bus "0 of the device, respectively, the first and second groups of information inputs of the second switch are connected to outputs and inputs of the second group of combinational adder respectively, the first and second groups of inputs of the adder Raman j-ro summing node K-th level (k = _{2, ..., Eog t m, j} = 1, ...,) are connected with the outputs of the second switches (2j-1) -ro and 2j-ro of the summing nodes of the (K-1) tier, the outputs of the first switches of all summing nodes and the output of the second switch (iog ^ nO-ro of the tier are connected to the inputs of the output register, controlling the inputs of the switches of the Xth tier (I = 1, ..., £ og _i and) are connected to the Eth input of the device settings. SU. ,,, 1149246> I