SU1376081A1 - Adding device - Google Patents

Abstract

The invention relates to the field of computer technology and can be used to build the arithmetic units of specialized computing devices leading to the processing of numbers in a sequential code. The purpose of the invention is to expand the scope by handling floating-point numbers. The device contains a counter 4, a pulse distributor 1, an order 2 switch and a group of elements 3. The pulse distributor produces a series of distributed pulses at its outputs. The number of outputs may vary depending on the size of the summation number. The switch of the order, depending on the order of the number, connects the codes of the distributor to the corresponding second inputs of the block of elements AND, the first inputs of which receive bits of a sequential number. Each bit, the pass through the AND circuit, enters the corresponding summing input of the pulse counter and increases its content by an amount equal to the weight of the bit. 2 Il. Q $ (L

Description

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The invention relates to computing and can be used to sum the consecutive binary numbers of arbitrary size and order that arrive one after another.

The purpose of the invention is to expand the scope by handling floating-point numbers. IQ

FIG. 1 is a block diagram of the device for addition; in fig. 2 is a timing diagram of the formation of pulses.

The device for adding contains 15 distributor 1 pulses, a switch 2, a group of elements AND JS, a counter 4, a clock input 5, an input 6 of the digit number, an input 7 order of the number, information input 8, 20 an input 9 of a reset, 10 outputs of the device , the outputs 11 of the pulse distributor, the outputs 12 of the switch, 2 order and 13, of the group of elements I 3.

The group of elements And 3 connects consecutively coming bits of numbers on informational input 8 to the corresponding summing inputs of the counter 4 pulses.

Pulse counter 4 is designed to sum the bits of the numbers supplied to its summing inputs. The pulses arriving at the first summing up of the counter input increase its content by one, by the second input - by two, by the third - by four, and so on in proportion to the power of 2.

All the blocks used in the device are standard computer components and can be implemented, for example, on integrated circuits of the 530 and 1509 series.

The addition device operates as follows.

Suppose that the sum of the summed numbers is equal to ten, and their output is 11.1–11. Before the start of the rabbi 1 pulses, a series of pulses are formed, distributed in time (Fig. 2). The number of these series depends on the code applied to the input 6 of the digit number. Series development always starts from the first output 11 of the distributor 1 pulses. For example, if the digit sum of the summed numbers is eight, then the pulse train you; - work on the outputs 11.1, 11 .2, ..., 11.8, if the digit number is ten, then the series are generated, on the outputs 11.1,11.2 ,. .., 11.10.

Switch 2 connects a group of outputs of a distributor of 1 pulses to the corresponding group of inputs of a group of elements I. The number of connected outputs of the distributor of 1 pulses is determined by a code specified by input 6 of the digit number and the code specified by The input is 7 times the number. For example, if the digit number is nine or about three, then the switch is connected to the outputs 11.1, 11.2, ..., 11.9 of the distributor 1 pulses to the inputs 12.4, 12.5, ..., 12.12 of the group of elements And 3, respectively. Thus, the order specifies the number of bits by which the highs of the pulse distributor 1 are displaced with respect to the second inputs of the group of IZ elements.

The group of elements And 3 connects consecutively coming bits of numbers on informational input 8 to the corresponding summing inputs of the counter 4 pulses.

Pulse counter 4 is designed to sum the bits of the numbers arriving at its summing inputs. Pulses arriving at the first summing input of the counter increase its content by one, at the second input - by two, by the third - by four, and so on. numbers 2.

All the blocks used in the device are standard computer components and can be implemented, for example, on integrated circuits of the 530 and 1509 series.

The addition device operates as follows.

Suppose that the sum of the summed numbers is ten, and their number is 0 5

0

0

The pulse counter 4 is reset to zero at input 9 of the device reset. Under the action of sync pulses arriving at the synchronization input 5, the pulse distributor 1 generates a series of distributed pulses at the outputs 11.1,11.2, ..., 11.10 (FIG. 2), since at the input 6 of the digit number there is a code of ten, equal to the number bits of summable number. A switch 2 on the order of the code of the number ten, present at the input 6 of the digit number, and the code of the number five, present at the input 7 of the order of the number, connects the outputs 11.1,11.2, ..., 11.10 of the distributor 1 pulses to the second inputs 12.6, 12.7, ..., 12.15. And 3. A group of elements. To the first inputs of this block, the information input of the device 8 sequentially receives bits of summable numbers. The first digit of the number under the action of a pulse at input 12.6 passes through the circuit And 3.6 and goes to the summing input 13.6 of the counter 4 pulses, increasing its contents by the value 2, the second bit through the circuit 3.7 enters the input 13.7 of the counter 4 pulses and increases its contents are at a value of 2, etc. The tenth bit through the scheme And 13.15 will go to the summing input 13.15 and will increase the contents of the bit of 4 pulses per

content

2

The bits of the second number arriving at the information input 8 are successively summed with the corresponding bits of the first number in the counter of 4 pulses, etc. Thus, the sum of the numbers arriving at the information input 8 of the device is accumulated in the counter.

If it is necessary to change the size and order of summable numbers, other codes must be submitted to input 6 of the digit number and input 7 of the order of the number.

Claims (1)

Invention Formula A device for adding, containing a group of elements AND and a counter, characterized in that, in order to expand the scope of application by processing floating-point numbers, a pulse distributor and a switch are introduced, the first and second inputs of elements AND of a group are connected to the corresponding outputs of the switch and with the information input of the device, respectively, the input of the device number of a width is connected to the control input of the pulse distributor and the first control input of the switch, the second control input of which Connected to the input of the order of the device number, the clock input of the device is connected to the clock input of the pulse distributor, the outputs of which are connected respectively to the information inputs of the switch: the outputs of the AND elements of the group are connected respectively to the inputs 11 of the counter bits whose reset input is connected to the reset input the devices, the outputs of the counter bits are the outputs of the device result. Fie.2