SU450168A1 - Batch multiplier - Google Patents

Description

one

The invention relates to the field of computing and can be used for parallel multiplication of one packet consisting of t numbers, another, third, etc., packets of / n numbers, while simultaneously producing t results of multiplication. Such a device can be used in processors for statistical processing of data (correlometers, spectrometers, digital filters), devices for matrix operations, etc.

A device for batch multiplication of numbers is known, comprising p blocks of receiving registers connected by outputs to the first inputs of the respective comparison circuits, and inputs to the corresponding information inputs of the device; clock generator, the output of which is connected to the input of the frequency divider and the input of the random number generator, each of the p outputs of which are connected to the second inputs of the respective comparison circuits; p — input matching schemes; up — input multiplying characters of numbers; reversible counters, the outputs of which are connected to the information inputs of the corresponding AND circuits, whose control inputs are connected to the output of a frequency divider; the outputs of the circuit "And connected to the corresponding outputs of the device.

In order to simplify the device for multiplying the numbers and increasing the speed of its operation, the outputs of the like comparison circuits are connected to the inputs of the corresponding coincidence circuits, the output of which is connected to the counting input of the corresponding reversible counter; the reversal control input of each of the counters is connected to the output of the corresponding number character movement scheme, the inputs of which are connected to the sign bits of the respective registers.

FIG. 1 shows the general scheme of the device; on fit. 2 - functional scheme.

A device for packet multiplication of numbers includes: blocks of 1 packet probability coding of numbers consisting of receiving registers of -digit comparison circuits and a sensor of one-digit random number;

2 clock pulse generator (GTI); block 3 of t, -input coincidence schemes, where n is the number of multiplied packets of numbers and characters multiplied; a divider of 4 pulses with a division factor of N (which determines the accuracy of the multiplication); block 5 of m reversible meters; block 6 of m output circuits; 7 generator of two random numbers RI and RZ; the input register 8 for storing the numbers of the first packet of the circuits 9 comparison

numbers; schemes of 10 multiplication of characters mod

3

2; schemes “OR 11; number comparison circuit 12; an input register 13 for storing the numbers of the second packet; switch 14.

The device works as follows.

In the receiving registers of blocks 1, the number of packets multiplied by the plant (as some of the packages can be scaled). At the clock points of time, a random number and packet numbers arrive at the comparison circuits of each block 1. As a result, a random sequence of pulses with a density proportional to the corresponding number will appear at each of the t outputs of block 1. All t-bie outputs of all n blocks 1 are fed to the nth n-input co-ownership scheme, the output of which goes to the counting input of a reversible counter. At the same time, in the same block the signs of the multiplied numbers are multiplied, the result of the multiplication of the signs determines the state of the control input of the reversible counter. After counting the N pulses of the GTI, block 6 opens and reads the result of multiplying n packets of m numbers.

FIG. 2 of the drawing shows a functional diagram of the device in the variant of multiplying two packets of numbers. Moreover, if a scalar appears as the numbers of the second packet, then it is inserted into the first register of block 9, the switch 14 is then set to position a. If the number of packets is more than two, their outputs are fed to the additional inputs of circuits 10 and 3, the remaining nodes of the device remain unchanged.

Subject invention

A device for batch multiplying numbers, containing p blocks of receiving registers connected by outputs with the first inputs of the respective comparison circuits, and inputs with the corresponding information inputs of the device; clock generator, the output of which is connected to the input of the frequency divider and the input of the random number generator, each of the p outputs of which are connected to the second inputs of the respective comparison circuits; p - input coincidence circuits and / 5 - input multiplication patterns of number characters, reversible counters, the outputs of which are connected to the information inputs of the corresponding AND schemes, the control inputs of which are connected to the output of a frequency splitter; the outputs of the AND circuit are connected to the corresponding outputs of the device, characterized in that, in order to simplify the device and increase the speed, the outputs of the similar comparison circuits are connected to the inputs of the corresponding coincidence circuits, the output of each of which is connected to the counter input of the corresponding reversible counter, the reverse control input of each of the counters is connected to the output of the corresponding pattern of moving the characters of the numbers, the inputs of which are connected to the sign bits of the corresponding registers.

-L-l.

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