SU477425A1 - Dividing device - Google Patents

Description

of the elements "NOT 14, 15, the element" OR 16, the delay element 17 by one cycle, the logical block of multiplication 18 and the register of the private 19, the second bit of which, counting from the younger one, works as a one-bit adder, and the rest - like the binary counter.

The proposed dividing device operates according to the static principle. The binary l-bit code of the dividers, given on the range of 0.5; 1 is written to divider 1 register. The binary p-bit code of the dividend y, given in the interval 0.1, is written in the register of the dividend 3. When the clock pulse from the generator 12 is fed to the groups of elements "And 5-9" on the first inputs of the comparison circuits 10 and 11 describe () -digit codes x and y, corresponding to the lower-order divisors and divisible y, and random (n-1) -digit numbers r and pi from different numbers are described to the second inputs of the comparison circuits 10 and 11 sensor outputs 13 evenly distributed random numbers.

If, as a result of a comparison (statistical testing), it turns out that (), then the comparison schemes 10 (11) refer to “1, otherwise -“ O. These statistical tests are repeated many times with a frequency set by the 12 clock pulse generator. The amount of these tests, necessary to represent the divider and divide in a probabilistic form with the required accuracy, determines the speed of the dividing device.

In the proposed device, a three-symbol probabilistic-impulse representation is implemented similarly as is known for speeding-up. The highest bit of the dividend code does not participate in statistical tests. The value of this bit indicates which of the two ranges is 0; 0.5 or 0.5; 1 is the dividend. The set of deterministic pulse sequence, coming from the output of the element "E 9", and pseudo-random sequence of pulses, coming from the output of the comparison circuit 11, is a three-character probabilistic-pulse sequence. The elements of this sequence are symbols with weights: 0, 0.5, and 1. If the dividend is in the range of 0; 0.5, the elements of the corresponding sequence are two characters with weights of 0 and 0.5. If the dividend lies in range 0.5; 1, then the elements of the corresponding sequence are characters with weights of 0.5 and 1. Statistical tests of the y-value of y in the full interval 0, L are replaced by tests of the (n-1)-bit value of y in the half interval. In this case, the number of elementary discrete levels corresponding to the unit of the lower order of the n-bit binary code is halved. To ensure that the absolute value of the error does not exceed the weight of the least significant bit of the binary

2.252

code, it is enough to carry out statistical tests, i.e., four times less than for a binary probabilistic imaginary presentation of a dividend with the same accuracy. Similar reasoning applies to the probability-impulse representation of the divisor. Since the divisor is specified in the interval 0.5; 1, then the value of the higher digit of the divider code is known in advance — it is equal to one. This allows not to use the high-order output 2 of the divider 1 register.

Thus, the divisor x is represented by a pseudo-random sequence of "ones and" zeros with weights 1 and 0.5, respectively, coming from the output of the comparison circuit 10 to the input of the element "NOT 14.

The elements "NOT 14, 15," OR 16 and delays 17 constitute a functional converter, from whose output (the output of the element "OR 16") to the input of logic unit 18 to 1

the step value presented in

binary probability impulse representation (sequences of "zeros and" ones with weights of O and 1, respectively), where x is the binary probabilistic representation of the divisor. In this case, the output element "NOT 15 through the delay element 17 to the second input element" OR 16 will receive the value (1-g). The delay element 17 allows to obtain the statistical independence of the pulse sequences arriving at the inputs of the element OR 16. As all divider 1 is removed from the register of the divider 1 to the comparison circuit 10, except bits 2, then from the output of the element NOT 14 to the input element "OR 16 a value of 2 (1-x) is supplied. The operation of the logical block of multiplication 18 is recorded in the table corresponding to the inputs and outputs - table 1 (a). Table 1 (b) shows the weights corresponding to the symbols of the factors and the product.

Character weight

Character code

The table uses the following notation:

ai is the input signal, aftercreeping from the output of the element “OR 16; ae is the input signal corresponding to the value of the high bit of the code of the divisible y; a is the input signal from the output of the Comparison 11 circuit; bi is the output signal arriving at the input of the first (lower) bit of the register of the private 19; 2 - output signal arriving at the input of the second bit (one-bit adder) register private 19.

The combined output signals bi and & 2 in, an arbitrary instant of time represents

Have

is the character code of the value

in 3x2x

free probabilistic representation.

Value - input to register x

The quotient 19 is half the quotient. If the output of a logical block

18 is the code 10, the corresponding symbol with a weight of 0.5, then the input of the first (lower) bit of the register 19 is received "one. If code 01 appears at the output of logic block 18, corresponding to a symbol with a weight of 1, then "zero" is input to the first bit, and "one" is input to the second bit. When calculating the number of bits of the register of the private 19, it is necessary to take into account the required number of statistical tests and that when entering the inputs of the register of the private

19 sequences of codes representing

the value it should accumulate

X number corresponding to the value -, i.e.

full private.

Thus, in register 19 a number is accumulated, which is closer to the quotient -

X

the more statistical tests performed.

Subject invention

A separating device containing dividend and divider registers, a clock pulse generator connected to the first inputs of elements “AND four groups of elements“ AND, the second inputs of which are connected respectively to the outputs of the lower bits of the register divider, outputs of the register of the dividend, first and second groups of outputs of the sensor of random numbers, two comparison circuits, two inputs of each of which are connected respectively to the outputs of the elements "And the first, third and second, fourth groups, the multiplication logic unit, the first input of which is connected not with the output of the first comparison circuit; its second input is connected to the output of the element

"And the second group connected by the second input to the high-order output of the dividend register, and the outputs of the logic multiplication unit are connected to the private register, characterized in that, in order to simplify the device, it contains the first element connected in series to the" NO "element connected to the first input element "OR, the second element is NOT and the delay element, the input of the first element is NOT connected to the output of the second comparison circuit, the output of the element OR is connected to the third input of the logical block multiplication, and the output of the delay element is below for prison staff to the second input "OR element.

.,. 477425

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