SU383042A1 - FORMER OF CODE COMBINATIONS - Google Patents

Description

one

The invention relates to automation and transmission of information and is intended to form code combinations of a unregistered code by single pulses, of which it uniquely corresponds to one of the combinations of the Russian or digital registers of the telegraph code MTK-2.

A coding device for generating code combinations by one-night pulses is known, comprising input and output curvatures, a shift register, a polling unit, a recurrent shift register, an output key, and the number of bits of the shift register and the time for forming one combination correspond to the number of input signals or the number of generated combinations.

The aim of the invention is to simplify the device and increase its speed.

To do this, the proposed shaper of code combinations includes a block for forming number of combinations in groups, performed on the schemes "OR, a block of forming the first combinations of groups, executed on the schemes" OR, and a shaper of the register feature, the inputs of which are connected to the corresponding input fields, and the output is the key input, the inputs of the schemes "OR of the block forming the number of combinations in the groups are connected to the corresponding input shells, the output of the last scheme OR the

and

is connected to the input of the polling unit, and the output of each of the remaining OR circuits is connected to the input of the corresponding bit of the shift register, the inputs of the OR circuit of the first combination of groups are connected to the corresponding input layers, and the output of each of these OR circuits is connected to the input of the corresponding bit recurrent shift register.

0 The invention is illustrated in the drawings.

FIG. 1 shows a diagram of the device; in fig. 2 - table of code combinations.

The device (see FIG. 1) contains input racks (-G-5) for supplying single pulses.

5 with a clock cycle G, a register feature generator 32 (performed, for example, on a trigger with separate inputs), intended to form register sign signals in a slot bit of code combinations

0 - “Ь (Russian register) or“ О (digital register), key 55 for forming with the tact Ga “in the output wedges of the bits of the T / i-H / Je digits, which unambiguously correspond to incoming files on the / -r-5 /

5 to single signals, a block number generation unit 40, executed in the schemes "OR, a block 49 forming the first combinations of groups, performed in five schemes OR, a poll unit 55,

0 to poll for 72 keys

33, forming on the output bus 56 a tracking pulse (the seventh bit of P code combinations) and resetting the recurrent shift register 57 (containing five bits) to form thirty-one code combinations generated using the fifth polynomial degrees of type shift register 63 (containing seven bits of & 4 H70), which is used as a delay line, and is also intended to determine the number of operating frequency cycles during which the first combination of group is converted into a combination corresponding to the input signal.

The device generates fifty eight eight-bit code combinations of a non-register code (combinations 000.000, 000.001 POLY, 110.111, 111.110, 111.111 are excluded). To form the first five bits of code combinations corresponding to the MTK-2 code, the set of possible input signals, equal to thirty-two, is divided into four groups, each of which contains eight combinations.

In general, the number of groups and the number of combinations in groups are selected from the condition of minimizing costs, taking into account the element base used. Moreover, depending on the element base used, i.e., the load capacity and the number of inputs in the elements constituting the bits of the shift register and the recuperative shift register, the units for forming the combination numbers in groups and the first combinations of groups can be excluded.

The shaper works as follows.

First set the register sign corresponding to the Russian or digital register.

When the code combinations of a signal with a tact T arrive at the input of the bus 10, the generator 32 of the register feature is set to the state corresponding to "O, and when the signal arrives on the input bus 31, to the state corresponding to" 1. The output signals from the imager 32 with a beat T are fed to the input of the key 33. Then the signal with the beat TI over one of the input buses / -30 (except for 10), is fed to the input of one of the circuits 41-48 "OR and to the input of the circuits 50- 54 "OR. If the signal arrives on one of the buses /, 9, 17, 24 to the input of the 48 "OR circuit, then the signal from the output of this circuit immediately with the cycle Ti arrives at the input of the polling unit 55, and when a signal arrives at one of the remaining plugs to the input of the block 40, a signal from the output of this block with a clock cycle TI records “b in one of the bits 64–70 of the shift register 63. The signal from the output of the register 63 with the cycle Tz is fed to the input of the block 55 of the survey.

The signals from block 49 are received with a cycle of GA to the input of the recurrent register 57 of the shift and

the first combinations of groups are recorded in it. The output signals from the register 57 with clock cycle GA are received at the inputs of the key 33.

Simultaneously and synchronously with the advancement “b” in register 63, the combinations are converted in the recurrent shift register 57 before the signal polling unit 55 arrives at the input (with a clock from the block 40 or a signal with a clock Gz from the shift register 63 |.

When forming the combinations corresponding to the first combinations of their groups, the signal from the output of the circuit 43 "OR arrives at the input of the polling unit 55, which then generates at the output a signal with a beat T, which arrives at the key 55, register 57 and the output bus 56 (bit Yat). In this case, at the output of the key 55, the first combination of this group is allocated and the register 57 is reset to the initial state - 00000.

When forming the remaining combinations of groups from block 40, the record "1 to one of the bits of register 63 is made, and from block 49, the first combination of the group is recorded in register 57. After that, simultaneously and synchronously with the advancement" 1 in shift register 63, the combinations are converted to the recurrent shift register 57 and a delay in the formation of the signal at the output of the discharge 70 of the shift register 63 for 1-6 cycles, and the interrogation of the key 55- "a / -7 cycles of the operating frequency (the cycle consists of 3 cycles TI, TZ n Gz time-related) during which the origin tpreobrazovanie kombipatsii the first group to the second to eighth.

From the output of the shift register 63, a signal with a clock cycle Gz is fed to the input of the block 55 of the poll 65, which generates a signal with the clock cycle T. After this, the key 55 is polled, the register 57 is reset to the initial state 00000, and the tracking pulse is generated on the bar 56.

At the same time, on tires 34-39, a combination is formed that uniquely corresponds to the input signal. This is where the formation of the code combinations ends.

Subject invention

A shaper code generator containing a shift register, the output of which is connected through the interrogation unit to the inputs of the recurrent shift register and output key, one output connection bus with the output of the interrogation unit, and the remaining output tires are connected to the output key, which is different in that and increase its speed, it contains a block forming the number of combinations in groups, performed in the schemes "OR, the block forming the first combinations of groups, performed on the schemes" OR, and the driver register Vågå characteristic whose inputs are connected to respective input schinami, and an output - to the input of key inputs

The “OR” block of forming the number of combinations in groups is connected to the corresponding input buses, the output of the last scheme “OR is connected to the input of the polling unit, and the output of each of the other schemes“ OR is connected to the input of the corresponding bit

the shift register, the inputs of the circuits OR of the first group combinations forming unit are connected to the corresponding input layers, and the output of these circuits OR is connected to the input of the corresponding bit of the recurrent shift register.