SU785865A1 - Device for converting parallel code into series one - Google Patents

Description

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The invention relates to the field of computing and can be used to convert parallel binary code into serial binary code.

Devices are known for parallel-serial and series-parallel conversion of a binary-coded-coded signal, for which the signals at the outputs of the pulse-distributor are formed using a binary counter and a matching circuit connected to the outputs of the binary counter. From the j-ro output of the coincidence circuit, the signal is removed when 15 only when the binary counter counts the number J in the binary system. The serial code is removed from the output of the OR circuit, whose inputs are connected to the outputs of the coincidence circuit 1. 20

Increasing the bits of the code being converted in the device complicates the binary counter and the matching circuit, and the required number of inputs to the OR circuit increases.

The closest technical solution to the invention is a device for converting a parallel code into a serial 2, containing a pulse generator, output 30

which is connected to the information input of the counter, the outputs of which are connected to the decoder. The outputs of the decoder are connected to the first group of inputs of the block of elements And, the second group of inputs of which is connected to the outputs of the register. The information inputs of the register are connected to the input buses, and the control input is connected to the output of the control unit. The outputs of the block of elements AND are connected to the inputs of the element OR whose output is connected to the output bus.

Parallel conversion (code; to serial is done by alternately connecting the register outputs through the elements and to the input of the OR element, and then to the output bus. The selection of the desired AND element is performed using a decoder and is determined by the counter state.

Claims (2)

In this device, an increase in the size of the codes being converted leads to an increase in the number of necessary elements of the AND block block and OR inputs equal to the number of bits in the code being converted; the counter size, since the number of the counter states must be no less than the number of bits of the code being converted and the number of decoder coincidence circuits and their complexity. The aim of the invention is to simplify the device by increasing the number of INPUT tires. This goal is achieved by the fact that the device for converting a parallel code into a serial one, containing a pulse generator, a counter, a decoder, a synchronizer and elements, And the first output synchronizer is connected to the installation input of the counter, whose input is connected to the output of the pulse generator, and the outputs the counter — with the outputs of the decoder, the outputs of which are connected to the first inputs of the AND elements, the outputs of which are connected to the inputs of the OR element whose output is the output of the device, contains n shift registers . The inputs of the j-ro shift register are connected to the inputs of the device (..., n;, j + n, ..., j + 7n), and the outputs of the shift registers are connected to the second inputs of the AND elements, the control inputs of the resolution of the shift registers are connected with the first inputs of the respective I elements, the control inputs for enabling the reception of the code are connected to the second output of the synchronizer. The drawing shows structures (On the device diagram for converting a parallel code into a serial. The device contains n shift registers 1, elements 2, generator 3, synchronizer 4, decoder 5, whose inputs are connected to the outputs of counter b, and outputs to the first inputs of elements And 2 and the control inputs of the resolution of the shift registers 1, the j-th output of the decoder 5 is connected to the first input of the element And 2 and the control input of the resolution of the shift of the j-ro register 1. The output of the j-ro register 1 t. Is connected to the second input of the j-ro element and 2. Element inputs and OR 7 are connected to the outputs of the elements AND 2 and its output to the output bus of the device.The output of the generator 3 is connected to the counting input of the counter B. The first output of the control unit 4 is connected to the installation input of the counter, and the second output is connected to the control inputs of code reception which are connected to the device input buses 8. Before starting work from the second output of the synchronizer 4, the control inputs of the reception of the code of the registers 1 receive a signal on which the registers are written to be converted into parallel With the first output and a control unit April 1 receives a signal at the counter 6 by which it is set to the initial state. The pulses from generator 3 to the counting input of the counterstag b change its state. As a result, the outputs of the decoder 5 receive signals that arrive at the first inputs of the And 3 elements, and are unlocked in turn from these elements to transmit information from the outputs of the registers -1 through the OR element 7 to the output bus. Signals from the outputs of the decoder 5 also go to the control inputs for the resolution of the shift registers 1, the shift pulse, is fed to the register 1 in the next clock cycle, after the information from its output through the selected element 2 has arrived at the input of the element OR 7. As a result, the frequency of the information shift in registers 1 n times less than the frequency of issuing a serial code at the output of the device bus. The number of elements AND 2, the number of inputs of the element OR 7, and the number of counter states are equal to the number of shift registers, which is less than the number of bits in the code to be converted. “Formula of the Invention A device for converting a parallel code into a serial one, comprising a pulse generator, a counter, a decoder, a synchronizer and elements, the first output of the synchronizer is connected to the installation input of the counter, the counting input of which is connected to the output of the pulse generator, and the counter outputs are connected with the inputs of the decoder, the outputs of which are connected to the first inputs of the AND elements, the outputs of which are connected to the inputs of the OR element, which is the output of the device, characterized in that , in order to simplify the device while increasing the width of the code being converted, it contains n shift registers, the j-ro inputs of the shift register are connected to the device inputs ... n; , j + n, ..., j + 7n), the outputs of the shift registers are connected to the second inputs of the AND elements, the control inputs of the resolution of the shift of the registers are connected to the first inputs of the corresponding AND elements, the control inputs of the code reception resolution - with the second output of the synchronizer. Sources of information taken into account in the examination of 1.Zra vk LRG 1162408, cl. G 06 F 5/04, 1964. 2. Authors th USSR certificate 549804, cl. G 06 F 5/06, 1975 (prototype). BI 8.8. Bsntnt Snszn - / . - / On Di s