SU1714585A1 - Universal operation unit - Google Patents

Abstract

The invention relates to computing and can be used in arithmetic devices for various purposes. The purpose of the invention is to expand the f: / functional possibilities by providing an operand shift towards the lower bits. The block contains a zero-zero bus, a synchronization bus 2, three control buses 3-5, and one-bit accumulating adders, each with t trigger 6, adder 7 mod 2, three elements AND 8 - 10, element OR 11, transfer scheme 12, element 13, transfer output 14, five switching inputs 15-19, operand input 20 and information outputs 21, connected between themselves functionally "2 ill. ^ 318 J9fig.1sl00 SP > &

Description

The invention relates to computing and can be used in arithmetic devices for various purposes. Operating units are known, which are parallel action adders containing n single-digit combinational adders and a result fixation register allowing to sum the n-bits, paudeaues. at the same time, the lack of data shift in the data is the sum of the arithmetic and logical devices (A) 1U), since in the ALU, the process is one of the Orobneibhydyyo. perform arithmetic and logical operations, some of which involve shifting information at the output of the adder using special shift registers. The closest to the proposed is an operating unit built on the basis of a accumulating adder which is taken as the basic block containing n single-bit adders made on the counting trigger, the sum of the torus on nrod 2, the switch consisting of two AND elements and the OR element, parallel transfer circuits, two control buses, a synchronization bus, and a zero bus with .. A disadvantage of this operating unit is the lack of a possibility of shifting to the right (in the direction of the gaps). The purpose of the invention is to expand the functionality by ensuring the shift of the operand. In the direction of the lower bits, the goal is achieved by the fact that the operational block containing n single-bit accumulating adders, each of which consists of a counting trigger, the adder nomod 2 of the first and second elements AND, OR element, transfer scheme, the first input of the first element AND is connected to the input of this bit of the adder, the first input of the second element AND is connected to the direct output of the counting trigger and the first input of the circuit The transfer of this bit, the outputs of the first and second elements And are connected to the first and second inputs of the element OR the output koToporo is connected to the first input of the adder mod 2 and the second input of the transfer circuit The second input of the adder mod 2 is connected to the third input of the transfer circuit, the output of the adder nrad 2 is connected to the t input. the counting trigger, the second inputs of the first, second and second elements are connected respectively to the first and second control buses of the operation unit, the information bit outputs of which are connected respectively to the direct outputs of the counting triggers, the output of the transfer circuit i-ro bit (where 1 1 , 2, 3, .. “, p-1) is connected to the third input of the transfer circuit (i + 1) -ro bit, the output of the n-th bit transfer circuit is the transfer output of the operation unit, the synchronization bus of which is connected to the inputs synchronization n counting triggers, inputs the installations of which are connected to the nulling bus of the operation unit, the third third two-input AND elements and the additional three-input AND element are additionally entered into it, the first input of the third element AND the i-ro bit is connected to the inverse output of the counting trigger (i + l) ro bit, The first input of the third element And the n-th bit is connected to the first switching input of the operating unit, the second inputs of the third element And are connected to the third control bus of the operational unit and the first input of the additional element And, the second input which is connected to the inverse output of the counting trigger of the first bit and the second switching input of the operating unit, the trough input of the additional element I is connected to the third switching input of the operating unit, the output of the additional element I is connected to the fourth switching input of the operational unit, the fifth switching input of which is connected to the third input transfer scheme of the first bit. The shift towards the higher bits is realized as for the base device by doubling the contents of the dripping adder. The counting mode with a given step is realized by applying counting pulses to the synchronization bus, presetting the counting step code on the operand inputs. Mode shift towards the younger. The bits is a mode that extends the functionality of the operating unit relative to the base device, and is implemented by subtracting from the contents the accumulating adder of the same contents, but shifted to the right. FIG. 1 shows the functionality of the operating unit diagram; FIG. 2 - connection of entrances and buses. The operating unit contains a zero bus; sync bus 2 first 3J second 4, third 5 control buses, n one-bit accumulating adders, each of which has a counting trigger 6, an adder 7 mod 2, a switch consisting of the first 8 and second 9 elements And, two-input element And 10 and the element OR 11, the scheme 12 of the transfer; an additional three-input element And 13, the output k of the transfer of the operating unit, the first 15, the second 16, the third. 17, the fourth 18, the fifth 19 switching inputs of the operating unit, the inputs 20 of the operand; information outputs of 21 operation units. The first input of the first element And 8 is connected to the input 20 of this bit of the operand, the first input of the second element And 9 is connected to the direct output of the grid trigger 6 and the first input of the transfer circuit 12 of the given bit, the second inputs of the first B and second 9 elements And connected to the first 3 and second control bus, respectively; the outputs of elements 8 and 9 are connected to the first and second inputs of the element 11, the output of which is connected to the first input of the adder 7 mod 2 and the second input of the transfer circuit 12, the second input of the accumulator, 7 mod 2 connected to the third input of the circuit Transfer s 12, direct outputs of counting triggers 6 are connected to information outputs 21 of the operation unit, outputs of transfer circuit 12 of i-ro discharge, besides the senior one, are connected to the third input of transfer circuit 12 (i-fl) TO discharge, output of transfer circuit Ca 12 most significant bit is the transfer output 14 of the operating unit, the output of the adder 7; mod 2 is connected to the T; input of the counting trigger 6, the synchronization bus 2 of the operation unit is connected to the synchronization inputs of the counting triggers 6, the zeroing bus 1 is connected to the inputs of the initial installation of the triggers 6, the first input of the additional i-ro bit in addition to the senior one, they are connected to the inverse outputs of the counting triggers 6, (i + 1) -th bit, the first input of the additional two-input element And 10 the highest bit is connected to the first switching input 15 of the operation unit, the second inputs of the additional two-input elements And 10 are connected to the third bus 5 control and the first input of an additional three-input element And 13, the second input of which is connected to the inverse output of the counting trigger 6. low-order bit and the second switching input 16 of the operation unit, the third input additional And 13 is connected to the third switching input 17 of the operating unit, the output of the additional three-input AND 13 and the third input of the low-order transfer circuit 12 are connected to the fourth 18 and fifth 19 switching inputs of the operating unit, respectively. The operating unit works as follows. To perform the functions of summation, shift to the left and shift. Right, output 1 of the transfer of the operation unit is connected to the third switching input 17 of the operation unit, the fourth 18 and fifth 19 switching inputs are connected to each other, the first switching input 15 is connected to the third control bus 5. Then the excitation function for the T-input of the trigger 6, the i-ro bit except the senior and the low order bits, the operation unit will be -m; (Xgoj.Ij VS | l4VS;, l5) © P; ,,. For the higher bit, the excitation function is of the form m (.,.,. The values of the output signals of the j-bit of the i-bit bit, except the high and low bit, will be P; P;.,. S; VPj.XjojIjVSiI VSit, xl5 ) VS; (X, jo .., VS;, l5). L of the most significant bit of the value of the signal of transfer is calculated by the formula RP RIM-S P V RPN (V V 14 V Ig) V VS CX onliVS I VIj). 717 The excitation function value for the low bit is determined by the expression T, (X, S,) © (PnS, l5) The transfer from the low bit will be associated with the transfer signal from the high bit P (, l5) (P, S , l5) (X, jl3VS, x) VS (X20, l5VS, l, VS, jl5), where I ,, Ig are control signals on the respective control buses. From the above expressions it is clear that there are three possible modes of operation of the operating unit: 1 1 Summation mode. The excitation function for T-5 Omladshy discharge in this case will be

Ti x

lOt

and the transfer from the low-order bit depends only on the value of the signal in the low-order bit of the operand and the state of the trigger 6 of this bit

P -, For the remaining bits Tj and P; will be

lt; Khzd; © R; m, (O

R; P, -, S; V.Pi., X2o; MS; X ,, - (2j

Expressions (1) and (2) correspond to the functions of a one-bit adder built on a synchronous T-flip-flop. The value of the output signal on the information bus 21 for any bit after the sync pulse on bus 2 is determined by the formula:

S; (t + & t) S; (t) @T;. (t),

which corresponds to the addition of binary digits S; (t) and taking into account the transfer of their bits P ,, from the mlad. By setting the input step code 20 on the input bus 20, it is possible to produce an invoice with a given step when applying a clock pulse over bus 2.

The shift to the left (in the direction of the higher bits). 1 (1, 1 15 rac) This mode is provided by switching to the first input of adders 7 modulo 2 values of the signals of the state of flip-flops 6 in the corresponding bits. In this case, when the clock signal is sent over bus 2, the number in the adder will be summed It is obvious that in order to implement this principle it is necessary to supply a logical unit to the switch (element I 10 ") of the highest bit, which is ensured by connecting the first switching input 15 to the third control bus 5, and to the low order transfer circuit 12 an onion of S, P, which is provided by an additional three-input element I 13 and a pair connection of inputs 17, 1 and 18, 19. Respectively, the proposed universal operating unit allows you to increase the size of operands almost unlimitedly. To do this, connect the inputs and buses in accordance with FIG. .2.

The control buses 3 and L, the synchronization buses 2 and the zeroings 1 are connected in parallel and are the inputs of the extended operating unit. The first switching input 15j of the j-ro operating unit, besides the senior one, is connected to the second switching input I6j + i (j-fl) -ro of the operating unit. The transfer output AND the j-ro operation unit, in addition to the senior one, is connected to the fifth 19 switching input (j4-l) -ro of the operation unit. The transfer output l4 of the senior operating unit is connected to the third switching input 174 of the lower operating unit, the fourth switch5, i.e. increasing it twice, which corresponds to the shift of the number to the left. S; (t + ut) S; (t) @S; (t) © P -, (t) Shift right mode. 1d 1. This operation is based on the principle of subtracting from the original S mix S of its half S (t + & t). S (t) - S (t) / 2. If we add the inversion of this number S (t) to the original number S (t), shifted to the right relative to the source Horoj, then we get half the original number, which corresponds to the shift of the right input 18 (the lower operating unit is connected with the fifth switching input The input operand is fed to the input information buses 20 of the operating units, and the information is removed from the output information buses 21 o. The first switching input 15 of the senior operating unit is connected to the third bus 5 control unit. Effects of each operational block The technical and economic efficiency of the proposed universal operational block is determined by the ability to perform on one device the functions of adder, counter, shift register right and left, as well as the possibility of increasing the size of the operands being processed. a block containing n one-bit accumulating adders, each of which consists of a counting trigger, modulo 2 adder, the first and second AND elements, the OR element, the n scheme The transfer, the first input of the first element I is connected to the input of this bit of the operand of the adder, the first input of the second element I is connected to the direct output of the counting trigger and the first input of the transfer circuit of this bit, the outputs of the first and second elements of I are connected to the first and second the inputs of the OR element, the output of which is connected to the first input of the adder on rood 2, the second input of the transfer scheme, the second input of the adder mod 2 is connected to the third input of the transfer scheme, the output of the adder on rood 2 is connected to the T-input of the counting trigger, the second inputs The first and second elements And are connected respectively to the first and second control buses of the operation unit, the information bit outputs of which are connected respectively to the direct outputs of the counting triggers, the output of the 1st bit transfer circuit (where i 1,2,3,4, ., n-1) is connected to the third input of the transfer circuit (i + l) -ro bit, the output of the n-th bit transfer pattern is the transfer output of the operating unit, the synchronization bus of which is connected to the sync inputs of the n-counting trigger, inputs initial installation which is connected to the w zero operational unit, characterized in that, in order to extend the functionality by providing a shift of the operand towards the lower bits, a third of the two two-input And elements and an additional three-input And element are additionally introduced into the Negro -ro bit is connected to the inverse output of the counting trigger (i + 1) -ro bit, the first input of the third element and the n-th bit is connected to the first switching input of the operating unit, the second inputs of the third element And is connected with the third control bus of the operation unit and the first input of the additional element I, the second input of which is connected to the inverse output of the first-stage counting trigger and the second switching input of the operation unit, the third input of the additional element I is connected to the third switching input of the operation unit, the output of the additional element And it is connected to the fourth switching input of the operating unit, the fifth switching input of the coordinator is connected to the third input of the transfer circuit of the first discharge.

Fie.2

Claims (1)

20 ₍ Formula of the invention) A universal operating unit containing p. One-bit accumulating adders, each of which consists of an estimated trigger, a sum of 25 matra mod 2, the first and second elements AND, OR element, transfer circuit, and the first input of the first element And connected to the input of this discharge operand of the adder, the first rear input of the second element And is connected to the direct output of the counting trigger and the first input of the transfer circuit of this discharge, the outputs of the first and second elements And are connected to the first and second inputs of the element And LI, whose output is connected to the first input of the adder in mod 2 and the second input of the transfer circuit, the second input of the adder in mod 2 is connected to the third input of the transfer circuit, the output of the adder in mod 2 is connected to the T-input of the counting trigger, the second inputs of the first and second elements And connected respectively to the first and second control buses of the operating unit, the information bit outputs of which are connected respectively to the direct outputs of the counting triggers, the output of the i-ro discharge transfer circuit (where i = 1,2,3, ..., n-1) connected to the third input of the transfer circuit (i + l) -ro discharge, the output of the transfer circuit of the ηth discharge is the output of the opera transfer. a unit, the synchronization bus of which is connected to the synchronization inputs η of counting triggers, the initial installation inputs of which are connected to the zeroing bus of the operating unit, characterized in that, in order to expand the functionality by ensuring the operand is shifted to the lower digits, η is additionally introduced into the negro third two-input elements * and And an additional three-input element And, and the first input of the third element And i-ro discharge is connected to the inverse output of the counting trigger (i + l) -ro discharge, the first the third input of the third AND element of the nth discharge is connected to the first switching input of the operating unit, the second inputs η of the third AND elements are connected to the third control bus of the operating unit and the first input of the additional element AND, the second input of which is connected to the inverse output of the counting trigger of the first discharge and the second the switching input of the operating unit, the third input of the additional element And is connected to the third switching input of the operating unit, the output of the additional element And is connected to the fourth switching the input of the operating unit, the fifth switching input of which is connected to the third input of the transfer circuit of the first category.