SU888106A1 - Device for raising to the power - Google Patents

Description

The invention relates to the field of digital computing and can be used in digital computers and specialized devices. A device for raising to the power fl is known, containing a group of adders, a dt shift unit and a control unit. The drawbacks of the device are relatively low speed and a significant increase in the volume of the apparatus with an increase in the power ratio. The solution to this technical field closest to the invention is device 2, which contains a group of duplicating blocks of the same type, a control unit, an argument bus, and an operand register, whose outputs are connected to the first inputs of the multiplying blocks, the first input is connected to the first output of the control unit and to the second inputs of the multiplying blocks. The disadvantages of the known device are relatively low speed, due to the inability to calculate the bits of the result at the time when not all the bits of the arguments and the greater complexity of the device arrived at the input of the device. The aim of the invention is to increase speed. The purpose of the invention is achieved in that the device contains a trigger of the initial state, the input of which is connected to the bus of the exponent and the third inputs of the multiplication blocks, the fourth inputs of which are connected to the output of the trigger of the initial state. The second and third outputs of the control unit are connected to the fifth and sixth inputs of the copying units. The second input of the operand register is connected to the output of the first multiplying block, the argument bus is connected 3 to the seventh inputs of multiplying blocks. Another difference of the proposed device is that in it the multiplying blocks contain a register of intermediate values, three adders, a control unit of the multiplying block, two control the trigger, the inputs and outputs of which are connected to the corresponding inputs and outputs of the control unit of the duplicating unit, the information input of which is connected to the output of the third adder, the first and second the inputs of which are connected to the outputs of the first and second adders, respectively; the output of the intermediate value register is connected to the first inputs of the first and second adders; an auxiliary register, the input of which is connected to the information output of the control unit of the multiplication unit, the first output of which is connected to the input of the intermediate values register and the first the control input of the first adder, the second output is connected to the first control input of the second adder, the third output of the control unit of the duplicating unit en with. the first control input of the third and the second control input of the second adder and the fourth output are connected to the second control input of the first and the second control input of the third adder. The second output of the node of the copying unit is connected to the installation input of the unit of the third bit of the first adder. The first input of the NfHOKHTenbHoro block is connected to the second input of the first adder, the second input to the third input of the register about intermediate values and the second input of the second adder, the third input to c. the first input of the control unit of the copying unit. The fourth input of the multiplex unit is connected to the second input of the control unit of the multiplying unit, the fifth input to the second input of the intermediate value register and the third input of the third sum of the matrices, the sixth input to the third input of the control unit of the multiplication unit, the seventh input to the fourth input of the control node multiplying unit, and the output - with the output of the auxiliary register. The drawing shows a block diagram of a device for exponentiation. The device contains a control unit 1 containing a 2q-bit signal distributor 2 (where q is the result size) and a five-bit signal distributor 3- In addition, the device includes a 2q-bit register of the It operand (X; right shift by one bit and having the properties of a multi-input reversible counter, the trigger of the initial state 5 and n identical multiplying blocks 6 (where n + 1 is the maximum operand unit size y). In each duplicate block 6 there are 7 intermediate values register having shift chains to the right for one bit, and having the properties of a multi-input reversible counter, is associated with the inputs of accumulating adders 8 and 9, the outputs of which are connected to the inputs of the accumulating adder 10, having a left-shift circuit by one bit. Moreover, the register 7 and adders 8, 9 and 10 each with 2q + 1, 2q + 3, 2q + 2, 2q + 6 bits, respectively, and since the bits of the indicated nodes do not coincide, the inputs of the remaining high-order bits are everywhere connected to the output of the first (sign) bit. For convenience, we consider the first (left) bits to be the first to be everywhere. In each i-th (i 1-p) duplicating block b, the outputs of the distributor 2 are cyclically shifted to the left by t (il) bits connected to the inputs of the register 7. Similarly, the outputs 2J-X of the bits of the distributor 2 (j 1, 2, .. ., q) are connected to the j-th inputs of the adder 9- The inputs of the adder 8 are connected to the outputs of the register. The output of the fifth bit of the distributor 3 is connected to the shift chains of registers, 7 and adder 10, the control unit 11 of the duplication unit implements the following system of switching functions. 23, 3.2 325D-a And 24, rf, 1 30, V329.2 34.2 2V 17 329,%, 1 ZM 9.1-9o ,. ° 2.1 ° zo, a) Sfl. 323Д-, 15 ZP, ЗЗо, ag9.1-Cho.gr 36.1 14.4 G 329.1 GO-ib, g-a24, iaij,) - a2 (), i. Esod V}, - 32.4, () 57.2 a2.4 (a ivafe) -a29, i-a5oi, 38 (, 2 3: 29,2-а50Д f3V -aa.i-ajoH. F3q.2 a4Q. i (a2Q.4va, o, 2) 4o, g 4 it Z-2., 2 o, l, 18 25.1 (27.1 9202 3272-) W 42 918 (320) ig, 19 -. r e0 ,, z- 2e, f b where indexes of arguments and functions coincide with the numbers of inputs and outputs of node 11 of the control of the multiplying block. Output information is formed at outputs 12, 13. To its input of 1 bit, the output of the 2 nd bit is distributed l 2 , inputs 15-18 are connected to the outputs of the four first bits of the distributor 3. The input bus 19 of the operand Y and the input buses 20, 202 of the operand X and the output buses 21, 222 (il) -ro ° are connected respectively to the inputs 22, 23, 232. and The outputs of the three most significant bits of the adder 10 are connected to the inputs 2Sj-27j, with the inputs 28 29 and 30, the outputs of the trigger 5 and the outputs of the control triggers 31 and 32 of this multiplier are connected. The output 33 of the node 11 of the first multiplier, block 6 is connected with the control input of the register 4. In addition, the outputs 3 of all multiplying blocks 6 are connected to the control inputs of the adders 9 and 10, and the outputs of the accumulators 9 are connected to the control inputs of the adders 8 and 10 36. The outputs 37 are connected to the control inputs of the register 7 and the adder. 8. Output 38 is connected to the installation input of the third discharge unit of the adder 8, the inputs of the control flip-flops 31 and 32 are connected to the outputs of the GE and Q, and the outputs 12, 13 are connected to the inputs of the auxiliary register tl, the outputs of which are connected to the output buses 21 and 212. intermediate result of this multiplying unit 6. The principle of operation of the device for exponentiation is that each multiplying unit 6 is squared of the intermediate result and, if necessary, multiplied by X, i.e. For example, the construction of the number X to the power of Y 13 is carried out according to the formula Z (((x) XY) x. Therefore, depending on the value of the corresponding digit of the operand Y, each multiplier unit 6 can work in one of three modes: 1J building the intermediate result in square; 2) squaring the intermediate result and multiplying by X; 3) multiplying by one. One or another mode of operation of the i-ro multiplier 6 is determined by the state of its controlling triggers 31 and 32, in which O and 1 are recorded in the initial state, respectively. Each i-ro multiplier is configured by triggering the initial state 5 and ( +1) -th digit of the operand Y, arriving in the (i-1) -th cycle of the input bus 19 in the inverse code. The third mode corresponds to the zero state of the control triggers. It is used when the operand Y contains zeros in the higher bits. In this case, in the first blocks 6, the number of which is equal to the number of zeros in the higher bits, the numbers of the operand X are transmitted from the input buses to the output without change, but with a delay equal to the delay in the appearance of the result at the output in the first two modes. The first unit of the number Y sets the trigger of the initial state 5 to one, which in the subsequent clock cycles succeeds the trigger 31 of the remaining multiplying blocks 6, and depending on what value O or 1 each takes, it is written to the trigger 32 digit " operand Y, this block 6 adjusts -w with for operation respectively in the first or second mode. Thus, the operation of the device for exponentiation can be clarified by examining the operation of one multiplying unit 6. In the initial state (the initial state setting circuit is not shown in the drawing} in all registers and totalizers O are written, and the control triggers 31 and 32 are in the state specifying a certain mode, since each multiplying block 6 is tuned to a certain mode earlier than the rest of the operands arrive in. In each k-th cycle of the 6th cycle in the control unit 1, unit 1 in the 26th bit distributor 2 and in k -M bit de allocator 3. In this case, the input bus lines 20 and 20 in redundant binary code with the numbers 1.0, 1 receive the next digits of the perandah X and the intermediate result, having a weight of 2, respectively, where i is the number of the multiplying unit 6. And + 1 corresponds to the presence of a signal on bus 20., -1 is the signal on bus 20, and zero is encoded by the absence of a signal on

white tires.

I

When block 6 operates in the first mode in each cycle, the digital input to the input buses 21 via the node 11 of the control of the multiplying unit controls in the third cycle the summation of the content, the adder 10 with the code of the adder 9 and in the second and fourth cycle - the summation of the contents of the adder 9 with the distributor code 2, in such a way that a direct code is added to the specified adders, if the digit is 1 at the time, or the additional codg if the received digit is 1. The totalizer code does not change, if the received digit is zero.

If block 6 is configured for operation in the second mode, then in the manner described above, the digit received on the input buses 20 controls in the first cycle the addition to the accumulator 10 of the contents of the adder 9 and the addition to the accumulator 8 of the register 7 (in the first block 6 this figure also controls receiving the code of the distributor 2 to the register), and the digit taken to the input buses 21 controls in the third cycle the reception of the adder code 8 and register 7 to the adder 9 to the adder 10 and the register code k and the adder 8 in the second and fourth clock code will distribute ate 2 on register 7.

When the duplicating unit 6 is configured for operation in the third mode, in the second cycle the first digit is set to the third digit of the adder 8,

if the 21-digit received on the buses is 1 or 1. In the third cycle, as described above, this digit controls the addition of the contents of the adder 10 with the code of the adder 8.

In addition, regardless of the mode in the fourth cycle, the control unit 11 of the multiplying unit, analyzing the three first bits of the adder 10, generates the next digit of the next intermediate result, and places it for temporary storage in register 1 (+1 is formed when in the three highest bits 001 or 010 is written, and -1 is written when I write Y or 101,

in the remaining cases, 0 will be generated. In the fifth clock cycle, the signal distributor 2 is shifted to the right, shift to the right by one bit of registers j and 7 and shifted by one

bit to the left of the contents of the adder 10. Moreover, when shifting in the adder 10, the value of the third bit is rewritten not only in the second but also in the first bit.

The operation of the device for exponentiation on a numerical example is illustrated by tables compiled for the first replicating unit 6, the mode number of which corresponds to the number of the table where X, and denotes the numbers received on the input buses 20 and Z denotes the numbers given out unit on the output tires 21.

Table 1

9

t z

See 9 P.S. 2 See 9

ten

.888106 Continuation of table 1

3

about

0101000000 000100

opoooooo

5 See 10 pp. 2

Tact

00010010000000

00000100000000 0010 0100

 cycle

3 cycle

t1

7 cycle

Tact 3 Sm, 10 k Z 5 See 10 notes Tact 1 X Pg. k Rs 2 Pr. C See 8 Pr, ti: See 8 See 10 See 9 See 10

000000000 f 001000000

001000000

yoooooooooooo

888106

12

Continued table. one

9 cycle

000000000 000010000 001010000

-00011000000 1111001000000011100100000000 ОО 1110010000000011001000000000 The present example is made for q q, i.e. starting from the fifth cycle, all the digits taken at the input of the computing unit 6 are equal to zero. Therefore, starting from the fifth cycle, the contents of all the registers and adders of this computing unit, except for the adder 10, cannot affect the result of the calculations and are not given in this table. The same applies to tables 2 and 3. 0100000000110000 0000000000000010000000 f-f0000000000000001000000 OOObbdObOOOOOOIIOQOOOO 0000000000000000000010000000 00000000000000 00000001000000 ooooooo & Table 1 February OOOOOO00000011000000 tsikl2 cycle January 1 0000000000100000 f401000000-00010000

IS

88810616

Continuation of table 2

17

Tact

2

00101001100110

3 See 10

k Z

11010011001100

5 Cm, 10

Tact

2

Tact

00100110011000

3 See 10

k Z

11001100110000

5 See 10

10 8 10

88810618

Continuation of table 2

6 cycle

5 cycle

11010011001100

00100110011000

8 cycle

7 cycle

8 cycle

7 cycle

11001100110000

00011001100000

Table 3

00000000000000

00001000000000 00000100000000 00000100000000 00001100000000 00000100000000

nineteen

00001000000000

5 See 10

Tact

5 cycle

00011000000000

10 V 00000000000000 00011000000000 10 tо 5 See 1000110000000000 Tact5 cycle 3 See 1011011000000000000) Z1 5. See 100011000000000000 Tact7 cycle 3 See 1011100000000000 t Zo "-" "-." - 5 See 10110000000000

As can be seen from the examples, the delay in the appearance at the output of a block of 6 corresponding digits of the result does not depend on the width q and is 4 cycles. at any q, in each bth cycle (C "1, 2, .... q + i), when a weight figure arrives at the input buses 21, the next result figure having a weight is formed at the output tires 21. Consequently, the full result at the output of the entire device will be obtained after receiving

888106

20 - Continued table. 3

0011000000000

00110000000000

11111100000000 00101100000000

the last digit of the operand X is delayed by the time T knJ, whereas the same delay for the known device is T, T ".... + T ....,

- l Ich fVl

febW R P The q of operand X, equal to 36, and the (n + 1) operand of Y, equal to 5, mean that the time required for obtaining the result is not less than 16 times.

If we compare the whole device operation time from receiving the first digit of the argument to issuing the last 1 11011000000000 6 cycle 00110000000000 1 11100000000000 8 cycle 11000000000000 1 n - - 0000000000000

2J

digits of the result, we obtain that, for the specified size, the proposed device surpasses the known speed by 9.2 times.

In addition to the increase in speed that is achieved for any Y, the proposed device also makes it possible to reduce hardware costs with large Y values.

Claims (2)

1. A device for exponentiation containing a group of duplicating blocks of the same type, control unit, the argument bus and the operand register, whose outputs are connected to the first inputs of multiplying blocks, the first input is connected to the first output of the control unit and to the second inputs of the upper units, characterized in that, in order to increase speed and reduce the number of equipment, it contains a trigger of the initial state The input is connected to the exponent bus and the third inputs of the multiplying blocks, the fourth inputs of which are connected to the trigger output of the initial state, while the second and third outputs of the control unit audio connected to the fifth and sixth inputs of multiplier units, the second operand register input connected to the output of the first multiplier unit is connected to the bus of the argument inputs seventh multiplier blocks. 2. The device in accordance with claim 1, 1, 1 and 2, that the multiplying unit contains the intermediate value register, three adders, the control unit of the multiplying unit, two control flip-flops, the inputs and outputs of which are connected to the corresponding inputs and outputs of the control unit of the multiplying unit informational 06 22 the input of which is connected to the output of the third adder, the first and second inputs of which are connected to the outputs of the first and second adders, respectively, while the output of the register of intermediate values is connected to the first inputs of the first and second adders and the intermediate register, the input of which is connected to the information output of the control unit of the duplicating unit , the first output of which is connected to the input of the register of intermediate values and the first control input of the first adder, the second output to the first control input second the adder, the third output with the first control input of the third and the second control input of the second adder, the fourth output with the second control input of the first and second control input of the third adder, and the fifth output with the installation input of the third digit one the first adder, while the first input of the multiplying unit is connected to the second input of the first adder, the second input is connected to the third input of the intermediate value register and the second input of the second adder, the third input is connected to the first input of the control node of the multiplier b Loka, the fourth input - with the second input of the control unit of the multiplying unit, the fifth input - with the second input of the intermediate value register and the third input of the third sum, the sixth input - with the third input of the control unit of the duplication unit, the seventh input - with the fourth input of the control node the multiplying block, and the output of the multiplying block is connected to the output of the auxiliary register. Sources of information taken into account during the examination 1. USSR Author's Certificate No., cl. G 06 F 7/38, 197. 2. USSR author's certificate number 425175, cl. G About F 7/38, 1972 (prototype.