SU1583939A1 - Device for multiplying polinominals - Google Patents

Abstract

The invention relates to computing and can be used in digital computing complexes and specialized signal processing devices. The purpose of the invention is to increase speed. This device implements the multiplication of polynomials represented as a list of pairs consisting of a non-zero coefficient and the corresponding exponent of the variable. A device for multiplying polynomials contains N coefficient registers, N multipliers, N blocks of shift registers, a switchboard, first and second registers, first and second groups of summing cells, a pulse shaper, and a clock generator. 1 hp ff, 2 ill.

Description

The invention relates to computing and can be used in digital computers and specialized devices.,

The purpose of the invention is to increase the speed of the device,

Figure 1 shows a block diagram of a device for multiplying polynomials; figure 2 - diagram of a summing cell.

The device contains n registers of 1 coefficients, p multipliers 2, n blocks of 3 shift registers, switch 4, first register 5, first and second groups of summing cells 6, second register 7, driver 8

pulses and 9 clock pulses.

The summing cell 6 (FIG. 2) contains a comparison circuit 10, four groups of AI elements, three switches 12, an adder 13 modulo two and

adder 14.

The device is intended to multiply polynomials. Polynom P (x) a

alo oo with so with so

, -f,

m

 a.x 1 is given by a list of pairs consisting of a zero coefficient and a corresponding exponent

When multiplying the polynomial P (x) n

and QOO

Z b.x

1g.

, „Submitted

a list of couples

B, hch), (bj.r ,,) ..... ,,,),

the result is a polynomial

to A (x)

Z with ,,

| H

T

which is represented by a list of pairs (cf hf) (° 2 pg.) < o (sk.), i, K.

When multiplying two sparse polynomials represented by a list of pairs, find the product of pairs and arrange them by the magnitude of the exponents (by the second component of the pairs) (combine all members with the same exponents.

The device works as follows OM0

Before the device starts operation, the coefficients of the polynomial multiplier Q (x) are written into the coefficient registers 1, the 8-impulse shaper is the Ke number py (not shown), where m is the order of the multiplicand polynomial; n is the order of the polynomial Q (x ).

In accordance with the frequency f of the generator 9 clock pulses, the coefficients of the first polynomial P (x) specified in the form of a list of pairs of nonzero coefficients and corresponding exponents of the coefficients of the second polynomial are stored in the information input of the device at the inputs of multipliers 2 and the coefficients of the second polynomial are stored in coefficient registers 1. Each of the registers 1 is divided into two parts, corresponding to the discharge of the coefficient and the discharge of the exponent, in multiplier x 2, the multiplication of pairs of coefficients is realized, and in each multiplier 2 consists of a two-input multiplier of two numbers and an adder. In this case, the adder implements the addition of the exponents of the corresponding parvs. The results of multiplication, i.e. pairs of numbers are successively recorded in registers 3 in accordance with the frequency of the generator 9 clock pulses

To the input of the shaper of 8 pulses, the pulses arrive at the frequency nrf, and in the series n is the order of the multiplier polynomial; f is the clock frequency of arrival of the multiplicand polynomial coefficients, and pulses with a frequency appear at the output, where K "nun.

Thus, after m cycles of operation of the device, the control input of switch 4 from the output of the former 8 receives a pulse of logical O

"N -.P- -JL-

0

five

0

five

0

five

0

45

0

five

As a result, information from the outputs of the group of shift registers 3 is fed through switch 4 to the inputs of register 5. At the next (t + 1) th cycle, the information is recorded in register 5 and goes further to the group of cells 6. At the same clock from the output of the imaging unit 8 the control input of the switch 4 receives a logical 1 signal (initial state) t as a result of which the outputs of the second group of cells 6 are connected through the switch 4 to the inputs of the register 50

The process of forming the resulting polynomial A (x), t, e0 is the process of arranging the pairs of coefficients by the magnitude of the exponents (by the second component of the pairs) with the union of all members with the same indicators in the first and second groups of summing cells 6.

The sum cell works as follows.

The comparison circuit 10 compares the exponents of two pairs. If the first indicator is greater than the second, then the output of the comparison circuit 10 is a combination of 10, otherwise the output of the comparison circuit is a combination of 01. If the exponents are equal, the output of the comparison circuit 1 0 is a combination of 11. In case of equality of indicators the degrees of the corresponding pairs on the first bit output of the coefficients of the summing cell there is a binary code of the sum of the corresponding coefficients, and on the first bit output of the cell degree indicator the degree factor code, on the second bit output the coefficient In other words, the first output of the cell coefficients discharge is a coefficient with a larger exponent, and the second output of the cell is a coefficient with a smaller indicator. At both outputs of the digits of the exponents, a kotz of the exponent, the corresponding coefficient, is added, which is the same as the output of the discharge of the coefficient.

The first 5 and second 7 registers, which are located at the outputs of the first and second groups of summing cells 6, respectively, are necessary for the device to function in the sorting phase. Phase I of the multiplication of polynomials takes place over a decade. The sorting phase (using the same frequency f) is performed in m-n cycles. Then, to obtain the resulting polynomial at the output of the device, m + m-n cycles are required.

In order to organize the operation of the device in the conveyor mode, the frequency of work in the sorting phase is increased n times, i.e. f c n-f. Consequently, at the output of the device, the resulting polynomial is obtained in m + m cycles after the first pair of coefficients of the polynomial P (x) arrives at the device input.

The proposed device has an increased speed in comparison with the known, which makes it possible to use it for real-time operation. In addition, the device also has lower hardware costs.

Claims (2)

1. A device for multiplying polynomials, containing n coefficient registers (n is the order of the multiplier polynomial), n multipliers, n blocks of shift registers, two groups of summing cells and a clock pulse generator, the first output of which is connected to clock inputs of n blocks of shift registers, information the inputs of which are connected respectively to the outputs of n multipliers, the first and second information inputs of which are connected respectively to the outputs n of the coefficient registers and information inputs of the device, characterized by the fact that In order to improve speed, a switch is entered into it, two registers and a pulse shaper, the output of which is connected to the control input of the switch, the first group of information inputs of which are connected to the outputs of the n blocks of shift registers, and the second group of information inputs of the first cells groups, which are the outputs of the device, the second output of the generator is so of the pulses connected to the input of the pulse generator and the synchronous inputs of the first and second registers, the outputs the switch are connected to the information inputs of the first register, the 1st and (1 + 1) -th outputs of which (, 4, K-2, where m is the order of the multiplicand polynomial) are connected by with the first and second inputs of the j-th summing cell of the first group (.,. K / 2-1), the first and second outputs which are connected respectively with the i-th and (i + l) -M informational inputs 5 of the second register, the first and К and informational inputs of which are connected respectively with the first and Km outputs of the first register, rth and (, g +1) -th outputs of the second register (, 3.5,. К-1) are connected respectively with the first and second inputs of the j-th summing cell of the second group (j l. ,,. К / 2) a five 2. The device according to claim 1, of tl and - that the summing cell contains a comparison circuit, four groups of elements, And, an adder, 0 modulo two, three switches, with the first groups of bits of the first and second information inputs of the cell connected respectively to the first inputs of the AND elements of the first and the second groups, the second inputs of which are connected respectively to the first and second outputs of the comparison circuit, the second groups of bits of the first and second information inputs of the cell are connected respectively to the first and second inputs of the comparison circuit and the first switch, the control input of which is connected to the control inputs of the second and third commutators, with the first input of the modulo two adder and with the second output of the comparison circuit, the first output of which is connected to the second input of the modulo two adder, the output of which is connected 0 with the first inputs of elements of the third and fourth groups, the outputs of which form the second output of the cell, the first groups of bits of the first and second information inputs of the cell are connected 5 to the first and second inputs of the second switch, the output of which is connected to the second inputs of the EI elements of the third group, the output of the third switch is connected to the second inputs of the elements of the fourth group, the outputs of the elements of the first and second groups are connected to the first and second inputs stroke, second groups of bits 7 | The second and first information inputs of the cell are connected respectively the adder, the output of which and the output of the first, with the first and second inputs of the third switch form the first output switch.   " jLLjpjnJ Euch t YOR & n IB / toff Р Е guvyd fue.l 2 VyhoZ