SU1388876A2 - Device for addressing storage units - Google Patents

Abstract

The invention relates to the field of computer technology and is an improvement of the device according to the author. No. 1298755. The purpose of the invention is to expand the functionality by implementing a remote control of a memory unit switch, which allows the device to be used to build autonomous memory systems with a large number of addressable memory blocks. The goal is achieved by introducing into the device, one of the m channels connected in series along the address circuits, the control inputs of which are connected in parallel, one OR in each channel. In addition, the validity switch of the memory block of each channel is connected by newly entered inputs to the address of its channel and to the recording and reset inputs of the device common to all channels, which allows remote control of the operation of the device, 1 sludge. (L

Description

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The invention relates to computing, is intended to address blocks in a memory system, and is in addition to auth. No. 1298755.

. The aim of the invention is to extend the functionality by implementing a remote control switch memory shelf unit.

The drawing shows a functional diagram of the device for addressing memory.

The device contains a group of switches 1, a group of adders 2, a group of comparison elements 3, a group of memory blocks 4, a group of elements OR 5 and has input 6 of the initial address of the device, output 7 of the final address of the device, input 8 of the current address of the device, input 9 of the device control mode , input 10 reset the device, input 11 recording device.

The device works as follows.

Preliminary control of memory blocks 4 is performed. To do this, a signal is set to zero at input 10 of the device reset. The 3Tot signal arrives at the first control inputs of switches 1 and sets them to zero. After that, a control signal of memory blocks 4 is fed to the input 9 of the control mode of the device, which is fed to the first input of the element OR 5 and passes to the first inputs of adders 2. The initial address is supplied to the second inputs of the first cyNwaTopa 2. Thus, sequential addresses are assigned to all memory blocks 4, and the code corresponding to the total number of memory blocks 4 is set at the outputs of the last adder 2. Next, the device operates in the mode of determining the operability of memory blocks 4 of the entire system. When accessing the memory, the comparison elements 3 compare the addresses from the outputs of the adders 2 and the address buses.

In the case of a present address, the addresses at the outputs of the K-th adder, where K 1,,,. , M (M is the number of blocks 4 in the group), with the incoming on address buses, on the K-m element 3 of the comparison, a signal appears that goes to the control input of the K-th memory block 4, i.e. the access occurs to the K-th block 4 of the memory.

After checking the operability of the K-th block of memory, the control device generates a single signal if the recording block is valid, and zero if not. The digital signal is fed to the input 11 of the device and sets the Kth switch to the opposite state corresponding to the operability of the unit. In the event that the Kth memory block 4 is inoperative, the Kth switch 1 remains

zeroed out. After checking the last memory block 4, the control signal is removed from the first inputs of the OR 5 elements and the outputs of the OR 5 elements remain single signals of the switches 1 corresponding to the operative memory blocks 4. Next, the establishment of a continuous address field corresponding to the serviceable memory blocks 4, and the operation of the device in the mode

block selection is similar to the specified.

The use of the OR 5 elements and the control Inputs in the switches 1 allows you to automatically control

states of switches depending on the malfunction of memory blocks 4, which makes it possible to use the device in autonomous computing systems.

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Claims (1)

Invention Formula five A device for memory addressing by author, no. 1298755, differing - -. Now, in order to expand the functionality by implementing a remote control of the memory unit switch, a group of OR elements is entered into it, with the output i-ro Ci 1 ,,,. ., rn) of the OR element of the group is connected to the control input of the i-ro comparison group element and to the first input of the i-ro group adder, the first input of the i-ro element OR subconnect groups  It is connected to the input of the control mode of the device, the second input of the i-ro ITM element of the group is connected to the output of the i-ro switch of the group whose information input is connected to the output of the i-ro the group comparison element, the recording and reset inputs of the i-ro switch are connected to the recording and reset inputs of the device, respectively. S 9 1011