SU1709324A2 - Interface - Google Patents

Abstract

The invention relates to computing, can be used in the construction of systems for the exchange of information between various devices of computer systems, such as processors and storage devices, and is an improvement of the known device according to ed. St. No. 1424022. The purpose of the invention is to increase the speed when a new communication channel is needed, since the change of logical addresses in the address registers takes place during one shift cycle and, in addition, the reliability of information transmission is increased by introducing a transmission information lock when a failure is detected. This is achieved by using the address shift registers, whereby the logical addresses in them by the error signal change during one shift cycle, and the information signal is also blocked on the exchange channel by the same signal. This makes it possible to form a new exchange channel without changing the logical addresses in the work programs of the subscribers participating in the exchange. 1 3. п. Ф-лы, 2 il.sls

Description

The invention relates to computing and can be used in the construction of systems for the exchange of information between various devices of computer systems, such as processors and storage devices, and is an improvement in the device according to the author. St. Mg 1424022.

The main invention describes an interface device comprising N interface matching blocks (N is the required number of subscribers) M address registers (M is the required number of communication channel between subscribers) and a matrix of switching blocks of dimension N x M, with the first information input and output The i-ro (, N) interface matching unit are respectively the iM information input and device output, the information output of the k-th (, M) address register is connected to the first information inputs / outputs of the switching blocks of the k-th matrix column, The information inputs and outputs of the switching blocks of the i-th row of the matrix are connected to the second information input and output of the 1st interface matching unit, respectively, the synchronization and initial setup inputs of all matrix switching units are connected to the configuration, synchronization and initial installation inputs of the device, respectively, the sampling inputs registers

addresses from the first to the M-th are connected to the device setup inputs, the second information inputs-outputs of the switching blocks of the matrix matrix column are interconnected, the control inputs of the switching blocks of the i-th row are connected to the control input of the 1st interface matching unit.

However, this device has a low speed in case of the need to organize an exchange channel when one of the switching blocks is disconnected.

The purpose of the invention is to increase the speed of the device. The goal is achieved by the fact that, in a device containing N interface matching blocks, a matrix of switching blocks of dimension N × M, the first information input and output i-ro (, N) of the interface matching block are information output and the i-ro input of the subscriber The output output and the second information input and output are connected to the control inputs with information outputs and inputs of the switching blocks of the i-th row of the matrix, the second information inputs / outputs of the switching blocks C-SL (, M) of the matrix column are interconnected, the inputs start installation, synchronization and settings of all switching units connected to the inputs of the initial installation of synchronization and device settings, respectively, entered M address shift registers, the inputs of the sample, synchronization and shift control are connected to the settings settings, synchronization and device error, respectively, information output k- th shift address register is connected to the first information input-output switching unit.

The switching unit contains a comparison circuit, the first input of which is connected to the information output of the k-th address register through the first information inputs-outputs, the second input is the information input of the block, the element 2Y-NOT, the first input of which is connected to the output of the comparison circuit, and the second input is a block setup input; a trigger; a setup input into a unit of which is connected to an output of an element 2I — NO; a synchronization input and a setup input to zero are the synchronization and initial setup inputs of a block; the ZI element, the first and third inputs Which are connected to the inputs of the settings and the presence of an error block, respectively, and the second input is connected to the inverse output of the trigger, the element is NOT, the input of which is the control input of the block, the first and second bus drivers, the sample inputs of which are connected to the output of the element ZI, and the information inputs and outputs are the information inputs and outputs of the block, the input of the transmission direction setting of the first bus driver is connected to the control input of the block, and the second is connected to the output of the HE element, the information inputs-outputs ne first- and second-bus drivers

0 are the first and second information inputs and outputs of the block, respectively.

The essence of the invention is as follows. Thanks to the fact that the address registers

5 are shift addresses, the logical addresses in them, by signal of the presence of an error, vary during one shift cycle. In addition, information on the exchange channel is blocked by the same signal. This allows you to create a new exchange channel without changing the logical addresses in the work programs of subscribers participating in the exchange, which increases the speed of the device and eliminates the possibility of further transmission

5 information with an error. New properties are provided without complicating the device,

FIG. 1 shows a block diagram of an interface device; in fig. 2 is a functional circuit switching unit.

0 The device contains (Fig. 1) N interface matching units 1, a matrix of switching units 2 of N x M, M dimension of shift registers 3 addresses, the first information input 4 and output 5 i-ro

5 (, N) of the interface matching unit 1 are the information outputs and the subscriber's i-ro input, the settings 6 inputs, the synchronization 7 and the 8 availability of a device error are connected respectively to the inputs

0 settings, synchronization and the presence of an error of the switching unit 2 and inputs for sampling, synchronization and shift control of the shift registers 3 addresses, input 9 of the initial installation of the device is connected to the inputs

The 5 initial settings of all switching units 2, the second information input 10 and output 11, the control output 12 of the i-ro interface matching unit 1 are connected to the information outputs and inputs and the control inputs of the switching unit 2 of the i-th matrix row, the first information inputs the outputs 13 of the switching unit 2 of the k-th (, M) matrix column are connected to the information output of the k-th shift

5 register 3 addresses, the second information inputs and outputs 14 are interconnected.

Switching unit 2 (Fig. 2) contains a comparison circuit 15, the first input of which is connected to the information output of the k-th address shift register, the second input is the information input of the block, the output is connected to the first input of element 2 OR-16, the second input of which The unit setup input, the output of element 2IL-HE 16 is connected to the installation input of trigger 17 in the unit, the synchronization input and input of the initial installation of which are the synchronization and initial installation inputs of the block, and the inverse output connected to the second input of the ZI element 18, the first input of which is connected to the setup input of the block, and the second is the input of the presence of a block error, the element NOT 19, the input of which is connected to the input of the transmission direction setting of the first bus driver 20 and is the control input of the block, and the output to the reference input the transmission directions of the second bus driver 21, the sampling inputs of the bus driver 20 and 21 are connected to the output of the ZI element 18, and their information inputs / outputs are the information inputs / outputs of the switching unit.

The proposed interface can be made using elements of various series. For example, as a comparison circuit 15, K555SP1 chips can be used, which allow the construction of comparison circuits with a multiple of four. As a trigger 17, a trigger can be used with installation in O, made, for example, on a K531TV9 chip. Elements 2ILI-NOT 16, ZI 18 and NOT 19 can be implemented, respectively, on the K155LI1, KM555LIZ, KM555LN1 microcircuits. Bus drivers 20 and 21 are used to connect or disconnect information sources and receivers to the buses, since their information outputs have three states and can be executed on K589AP16 chips. Registers 3 can be executed on K155IR1 shift registers with connecting on the output of K155LP8 microcircuits, which have three states, 4JO ensures that registers are disconnected from bus 13 after tuning. The interface matching unit 1 is shapers (used to match the levels of signals from subscribers), the number of which is determined by the number of information and control lines necessary for the communication of devices. These blocks can be made using ECL-TTL (K500PU125), TTLESL (K500 PU 124), KMDP-TTL (K176P1, K564PU), TTL-KMDP (K155LNZ, K155LN5) and

others

The device works as follows.

In the initial state in the k-th shift register 3 addresses recorded logical address

information buses of the k-th column of the switching matrix.

In the operation of the device, you can select the configuration phase and the exchange phase. The first phase is to tweak those channels.

0 communications, which are necessary for the exchange of information between subscribers in the exchange phase. At the same time, the device can be configured and then operate during the phase of the exchange of M communication channels. And communication

5 between any two subscribers, M can be formed in various ways by connecting subscribers to any kth pair of connecting buses from M possible pairs.

0 During the setup phase of the communication channels, a zero signal comes through the setup line 6, which acts throughout this phase, through the ZI element 18 in the switching unit 2 this signal goes to the sample inputs of the first 20 and second 21 bus drivers. At the same time, their outputs are transferred to a high-impedance state, which prohibits the transmission of information through the switching unit 2. In order to prepare the device for setting up communication channels, a single impulse is issued via line 9 of the initial installation, which resets the trigger 17 to the zero state. In the tuning phase, the signal arriving along setup line 6 from the registers 3 addresses via information buses 13 receives the logical addresses of the matrix columns. At the same time, subscribers, between whom it is necessary to organize an exchange, issue the same logical

0 is the address of the k-th information bus 13. At the same time, the second information inputs / outputs of the switching unit 2, connected to the second input of the comparison circuit 15, receive the logical address from the k-th bus 13

5 of the register 3 addresses, and at the first input of the comparison circuit 15, the logical addresses that determine the exchange channel are received from the subscribers via the information bus 11. In the comparison circuit 15 of each switching unit 2, the logical addresses arriving at its inputs from the k-th register 3 addresses and the 1st subscriber are compared. If the addresses at the output of the comparison circuit 15 do not match, a zero inequality signal is generated, which is fed to the first input of element 2 OR-LE 16, which, if there is a zero signal on the tuning line 6, generates a single signal at the output. This signal is fed to the synchronized input of the trigger 17 and sets it to the one state by the clock signal received via the synchronization line 7.

Upon completion of tuning, a single signal is set up on tuning line 6, which disconnects the 3 address registers from the information bus 13 and, through element 2 OR-NOT 16, prohibits further changing the state of the trigger 17. As a result of the tuning in the zero state, the trigger 17 of those switching blocks 2 remains , to the inputs of the comparison circuits 15 which receive the same logical addresses from the k-th register 3 addresses and the i-ro subscriber. The triggers 17 of the remaining switching units 2 will be set to one and the zero signals from their inverse outputs through the ZI elements 18 will be fed to the sample inputs of the first 20 and second 21 bus drivers, prohibiting the exchange of information. If the trigger 17 stores the zero state, then the single the signal from its inverse output, after removing the zero signal on line 6 of the tuning and the absence of the zero signal of the presence of an error, converts the output of the ZI element 18 into a single state and thereby opens the bus driver 20 and 21 for obm on, i.e. it connects subscribers to information buses 13 and 14. The direction of information transfer through the first 20 and second 21 bus drivers is set using control output 12. With a single signal at output 12, information is transmitted from information output 11 to the first information input / output 13, and from the second information input / output 14 via the second bus driver 21 - to information input 10.

In the second phase, the exchange will take place over the communication channels that were configured in the first phase. So, for example, if in the setup phase a communication channel was formed between the i-th (, N) and j-th (, N,} subscribers through the information buses of the k-th column of the switching matrix, then the exchange takes place in the following way. From 1- first subscriber (Aj) information through the i-th block 1 interface matching (BSI |) enters the block 2 of the switching of the i-th row of the k-th column of the matrix (), and then the block 2 of the switching of the j-th row of the k-th column through the j-th interface block 1 (BCl / Ij) to the information inputs (outputs) of the subscriber's j-ro (Aj), i.e.

Ai - BSI) - BKiK - BKjK - BSI - Aj.

In case of failure of one of the switching blocks 2 used during the exchange (AI or BI | k), the device allows you to organize a communication channel through another g pair of information buses (, M, g k. In this case, if a fault is detected on line 8, error, a zero signal is set, which, through element ZI 18, enters the sampling inputs of the first 20 and second 21 bus drivers and blocks further information transfer. The zero signal on the error line 8 also goes to the synchronizing control inputs of the register shift 3 ad The word and logical addresses in the address registers 3 are shifted along the synchronization signal 7 to the synchronization inputs of the registers, which leads to a change in the logical addresses of the exchange information buses and allows the exchange to take place over a new communication channel. For example, after changing the address, the previous way of exchanging information between iM and JM subscribers can be written as follows: Ai - BSI | - БК | к + 1 - БКJk-n - Аь

To organize the exchange via a new communication channel, there is no need to change the logical addresses in the work programs of the lgo and j-ro subscribers, it is only necessary to repeat the setup phase and proceed to the exchange via the newly organized channel.

Claims (2)

1. Interface device according to ed. St. Ms 1424022, characterized in that, in order to improve device performance, the error presence inputs of all switching units and the input address shift control input are connected to the device error input input, the address register synchronization input is connected to the device synchronization input. 2. Device pop. 1, characterized in that the switching unit contains a comparison circuit, a trigger, an AND element, an OR-NOT element, an NOT element, two bus driver, information inputs, the outputs of which are respectively the information inputs and outputs of the block, and the inputs-outputs the first and second inputs-outputs of the block, respectively; the first, second and third inputs of the And element are connected respectively to the trigger output, the setup input and the block error input, and the output to the sample inputs of the first and second bus drivers; audio transmission is connected via the NOT element with a control input unit and the input specifying the first direction of transmission bus shaper, the output of which the input is connected to the input circuit. . comparison, the second input and output of which are connected respectively with the information input of the block and the first input of the element OR NOT HE, the second 71. input and output of the block connected to the setup input and the trigger setup input, the sync input and the reset input of which are the synchronization input and the input block installation. 2.: / 9.2