RU1784984C - Conjugating device - Google Patents

Abstract

The invention relates to the field of computer technology and can be used to build an information exchange system between various devices of computer complexes, for example, between computers and external subscribers. The aim of the invention is to reduce the reconfiguration time of the device during the organization of the multiplex mode of information exchange. The interface device comprises matching blocks of the interfaces of the first and second groups, a first matrix of dimension NxK KE, a second matrix of dimension MxK KE, N + K memory blocks and N + M decoders Each FE contains two AND elements and the bus driver of the FE is tuned for switching when a single signal from the output of the decoder is received at the enable input during the setup phase. At the same time, the device can tune and then function in the phase of the exchange of K communication channels. 1 s.p. 2-silt

Description

The invention relates to the field of computer engineering and can be used to build a system for exchanging information between various devices of computer complexes, e.g., computers and external subscribers.

Known devices that perform the functions of the interface between several processors, input-output devices and containing matching units, peripheral processors, a cross-switching matrix and peripheral storage devices (Multiprocessor systems and parallel computing. M: Mir, 1976, Ch 1)

The disadvantages of the known devices are their complexity and high hardware costs.

A device for interfacing is known, comprising two groups of interface matching blocks, the first input and output of each of which are connected to the corresponding information inputs and outputs of the device, a tuning unit and a matrix of switching elements, the first inputs and outputs of switching elements being connected to the matching blocks of the interfaces of the first groups, and the second inputs and outputs are connected to the interface matching units of the second group.

The disadvantages of this device are low reliability and functionality, i.e., wetness.

Closest to the invention in technical essence is an interface device comprising two groups of N and M interface matching units

X

os

Ј

:

a b

accordingly, the information inputs and outputs of each of which form the information inputs and outputs of the device, K address registers, information outputs of which are connected to K information buses, the first and second matrix of switching elements with dimensions of (NxK) and (MxK), respectively, and the control inputs and the outputs of all the switching elements are connected to the control buses, and the information inputs / outputs of all the switching elements are connected to the information buses.

When operating this device, it is assumed that symbolic names are issued from computers and from external subscribers. To the corresponding information inputs, their output can be made both in software and in hardware. With the software method for setting up the interface device, minimal additional hardware is required, but this method will be significantly less time-consuming than the hardware method of setting. With the hardware configuration method, significant hardware costs are required for issuing symbolic names in each computing device individually connected to the interface device. To coordinate their work during the setup of communication channels, synchronization of their operation modes is required, which leads to duplication of a significant part of the equipment in each device and to an increase in the time for signal transmission via the interface. The use of the above devices for interfacing ultimately leads to overhead in the apparatus and to an increase in the time delays of signal transmission.

The purpose of the invention is to reduce the time of reconfiguration of the device when organizing a multiplexor mode of information exchange.

The goal is achieved in that in the device for the interface, containing two matrices of switching elements and two groups of blocks matching interfaces, the first information inputs and outputs of blocks matching interfaces of the first and second groups form the first and second groups of information inputs and outputs of the device, the second information the input-output and output of the 1st coordination block of the interface of the second group (i 1, M) are connected respectively with the first information inputs and outputs and control inputs of the switching of the first row of the second matrix, the second information inputs and outputs of the switching elements J-ro of the second matrix column Q 1, K) are connected via the j-th information bus 5 of the device with the first information inputs and outputs of the switching elements of the j-ro column of the first matrix, the control inputs of which are connected via the jth control bus with the control outputs of the switching elements of the j-ro column of the second matrix, the second information inputs and outputs and the control outputs of the switching elements of the ith row of the first matrix (p 1,

5 N) are connected respectively with the second information input-output and the input of the r-th block matching interface of the first group, the outputs of the matching blocks of the interfaces of the first group and inputs

0 matching blocks of the interfaces of the second group respectively form the groups of control outputs and inputs of the device, the tuning inputs of the switching elements of the first and second matrices are connected

5 with the device settings input, an address counter, memory units and a group of decoders are entered, the counter reset input connected to the device reset input, the input for increasing the contents of the address counter

0 is connected to the setup input, the information output of the address counter is connected to the address inputs of the memory blocks of the group, the information outputs of which are connected to the inputs of the corresponding

5 group decoders, the address input of the switching element of the nth row and the j-ro column of the first matrix is connected to the jth output from the rth decoder of the group, the address input of the switching element of the 1st

0 rows and j-ro columns of the second matrix are connected to the jth output of the (N + l) -ro decoder of the group, and the switching element contains the first element And, the second element And and the bus driver, the first and second

5, the information inputs and outputs of which form the first and second information inputs and outputs of the switching element, the first input of the first element And is the address input of the switching element, the configuration input is connected to the second input of the first element And, the output of which is connected to the sampling input of the bus driver and the first input of the second element I. the second input

5 of which is connected to the input of the job direction of the bus driver and forms the control input of the switching element, the output of the second element And forms the control output of the switching element.

In FIG. 1 shows a block diagram of a device; in FIG. 2 is a functional diagram of a switching element.

The interface device (Fig. 1) contains two groups of interface matching units 1 (the first group of N blocks, the second of M blocks), two matrices of switching elements 2 (the first of NxK elements, the second of MxK elements); N + M memory blocks 3, a group of control outputs 4, a first group of information inputs / outputs 5, a group of control inputs b, and a second group of information inputs / outputs 7. An output and a second information input / output of the 1st block coordination interface 1 of the second group (I 1, M) are connected respectively to the control inputs and 8 and the first information inputs and outputs 9 of the switching elements 2 of the 1st row of the second matrix. The control outputs 10 and the second information inputs and outputs 11 of the switching elements 2 j-ro columns of the second matrix 0 1, K) are respectively connected via je control buses 12 and information buses 13 with control inputs 8 and the first information inputs and outputs 9 commuting elements 2 j-ro columns of the first matrix.

In FIG. 1 shows the setting input 14 and the reset input 15 of the device. The switching element 2 contains (Fig. 2) the address input 16, the element 1/1 17, bus driver

18 and element 19. The address inputs 20 of all memory blocks 3, the information outputs of which are connected to the inputs of the corresponding decoders of group 21, form the output of the address counter 22 (Fig. 1).

The proposed interface may be implemented using elements of various series. So, for example, as the first element And 17 microcircuits K155LE1 can be used. The memory blocks 3 can be implemented on K541RU2 microchips and the decoder 12 on K555ID4 microchip. The bus driver 18 is used to disconnect or connect sources and receivers of information to the buses, as their information outputs have three output states. Bus driver 18 can be implemented on the chip K580BA86. To control the operation of the K580BA86 chip, there are two inputs: an input that controls the crystal sample (in the description it corresponds to a sample input) and an input that determines the direction of information transfer (in the description, the direction setting input). Second Elements And

19can be implemented on microchips

K155LN8. Elements of these microcircuits have three output states and two independent inputs, one of which is the control (in the description it corresponds to the first input) and the other is information (in the description the second input). At zero at the control input, the output of the element has a high-resistance state, and at unity it is transmitted to the output of the status of the information input. Interface matching blocks 1 are shapers (they are used to match signal levels from various devices of computer complexes, the number of which is determined by the number of information and control lines required for devices of the computer complex). These blocks can be performed using ESL-TTL (K500PU125), TTL-ESL (K500PU124), KMDP-TTL (K176PU1, K56PU4), TTL-KMDP (K155LNZ, K155LN5) level converter circuits and others.

The device operates as follows. In the initial state, in the memory blocks 3, a switching program is written in the form of a sequence of symbolic names to form communication channels.

In the operation of the interface device, a tuning phase and an exchange phase can be distinguished. In the setup phase, those communication channels are formed that are necessary for the exchange of information between computing devices in the exchange phase. At the same time, the device can tune and then function in the phase of the exchange of K communication channels. Moreover, the connection between any two computing devices can be formed by K in various ways by connecting them to the same pair of connecting buses from the possible K.

Before the operation of the interface device, a reset signal is issued to the reset input of the device 15, which sets the address counter 22 to the zero state.

During the setup phase of the communication channels, a zero signal is received at the setup input 14, which acts throughout the entire setup time and is supplied through the And 17 element to the sampling inputs of the bus driver 18 and And 19. Under the influence of the zero signal, the output of the And 19 element and the inputs - the outputs of the bus driver 18 are transferred to a high-impedance state, while the transmission of information through the switching element 2 is prohibited.

a zero tuning signal is supplied to the input of the address counter 22 and increases the contents of the address counter 22, setting the 1st address.

From the output 20 of the address counter 22, the 1st address is supplied to the address inputs of the memory blocks 3. From the information outputs of the memory blocks 3, the input to the decoder 21 will receive a symbolic signal corresponding to the setting phase. As a result of decryption of the symbolic name in the decoder 21, the corresponding output will be one, and the remaining outputs will have zeros. This single signal is supplied to the address input 16 of the switching element 2 of the 1st row of the j-th column and then fed to the first input of the first element And 17 and thereby adjusts the switching element 2 of the 1st row to work. In this case, the switching element 2, which receives a single signal, will be prepared for the transmission of information between computing devices.

Zero signals from the remaining outputs of the 1st row decoder 21 are supplied to the address inputs of the remaining switching elements 2 of the i-th row, which are thereby disconnected from the information buses 13.

At the end of the setting, a single signal is set at the input of the setting I4, which is fed to the second input of the first element And 17 throughout the entire exchange time. On the first input of element And 17, depending on the switching program, one or zero signals are supplied from the outputs of the decoder 21. When a zero signal arrives at the first input of the And 17 element, a zero signal is generated at its output, which is fed to the sample inputs of the bus driver 18 and the first input of the And 19 element, prohibiting the exchange of information. Upon receipt of a single signal at the first input of the And 17 element, the output of the And 17 element is brought into a single state. A single signal is fed to the sampling inputs of the bus driver 18 and the first input of the And element 19 and thereby opens them for information exchange, i.e. the connection of computing devices to information, buses 13 and control buses 12.

The interface device provides the formation of communication channels between pairs (computer - external subscriber), while both information and control signals are switched. In each switching element 2, information is transferred between the first 9 and second 11 information inputs / outputs in a controlled manner. The direction of information transmission through the switching element is set by the signals arriving at its control input 8 and then at the input

setting the transmission direction of the bus driver 18. With a single signal at the control input 8, information is transmitted in the direction from the first information input-output 9 to the second 11, and when

0 zero signal from the second information input-output 11 to the first 9.

In the exchange phase, information will be exchanged over the communication channels that were formed in the setup phase. So, for example, if during the setup phase a communication channel was formed between the 1st computing machine (VM) and the r-th external subscriber (VA) through the information and control buses of the j-ro column, then the control signals will be received via the following path: control input 6, input and output of the 1st coordination unit of interfaces 1 of the second group, control input 8, second element 1/1 19, control output 10

5 switching element 2 of the i-th row of the J-ro column (K3ij) of the second matrix, j-control bus 12, control input 8, the second element And 19, control output 10 of the switching element 2 of the 2nd row of j-ro

0 column (CEP) of the first matrix, input and output of the nth matching unit of interfaces 1 of the first group, information output 4. With a single signal at the control input, information will be transmitted

5 from VM to VA along the following path: information input-output 7, first input-output and second input-output of the interface matching unit 1 of the 1st row of the second group, the first information input-output 9,

0 bus driver 18, second information input-output 11 KE1), j- information bus 13, first information input-output 9, bus driver 18, second information input-output 11 K3pj,

5 the second input-output and the first input-output of the interface matching unit I of the first group; information input-output of the 5th row. When the signal at control input 6 is zero, information will be transmitted

0 from VA to VM only in the reverse order of following the above path.

If it is impossible to form a connection between the 1st VM and the r-th VA through the j-th information and control buses due to

5 of one of the switching elements K31J of the first matrix or K3pj of the second matrix, the device allows for similar communication through any other r-th information and control bus (r 1, K; r; J). It could be

achieved by changing the symbolic names in the switching program of the corresponding interacting devices. The functions of the j-x buses are not lost. They can be used for switching any other pair of devices of the computing complex to establish communication between which operable switching elements are not used.

The technical and economic effect is concluded as follows. The use of the proposed interface device allows to reduce the reconfiguration time in computer complexes with a communication system exchanging information in multiplexed mode, as compared to using a prototype device for this purpose.

The device reconfiguration time is mainly determined by the number of time cycles of all the necessary signals. The number of time cycles for reconfiguration in the prototype device is determined by the following signals: 1. issue a reset and the start of the setting, 2. give a symbolic signal to them, 3. give a synchronization signal, 4. give the end of the setting. A total of 4 time cycles is obtained, and for the proposed device only 2 cycles are required: 1. give the beginning of the setting, 2. give the end of the setting. The reset signal in this device is common and is given to the entire device before starting work. Thus, the changeover time is reduced by / 9 4 t / 2 g 2 times .-

In addition, the proposed device can significantly simplify the circuit and reduce hardware costs. The hardware costs of the interface device are mainly determined by the number of. Switching elements (N + M) K. The number of switching elements in the prototype device and in the proposed device is the same, and the complexity of the switching elements 2 themselves largely depends on the bit size L of the transmitted information. In addition to switching elements, N + M memory units and N + M decoders are additionally introduced in the proposed device. The hardware costs for the prototype will be obtained in the form of the formula Si ЗБСИ + Зкэ + ЗРГ + Зсх cp tr, where ЗБСИ is the cost of matching blocks of interfaces, Зкэ is the cost of switching elements, ЗРГ is the cost of registers, 3cx.cp.rp. - costs of comparison schemes and triggers. The hardware costs for the proposed device Zg are ZBSI + Zke + Zzu.sd., where 33.sup.sh is the cost of memory units and decoders.

Thus, hardware costs at N M K are reduced in

3, (N 4-M) 21 + (M + NT) K- (2L 4-1} + K L + (M + N) PoFK + M) R-gj - (N + M) JL + (M + (L + 0 + (M +

- - times

So, for example, for L 8, N 24, the value of R is:

164-109224

21 16

1.3 times.

Claims (2)

Formula of Invention 1. An interface device comprising two matrix of switching elements and two groups of interface matching blocks, the first information inputs and outputs of the matching blocks of the first and second group interfaces form the first and second groups of information inputs and outputs of the device, the second information input and output, and the output J-ro of the interface matching unit of the second group (j 1, M) is connected respectively to the first information inputs / outputs and control inputs of the switching elements of the ith row the second Matrix, the second information inputs are the outputs of the switching elements of the j-ro column of the second matrix (j 1. K) are connected through the j-th information bus of the device with the first information inputs and outputs of the switching elements of the j-ro column of the first matrix, the control inputs of which are connected through the Jth control bus with the control outputs of the switching elements of the j-ro column of the second matrix, the second information inputs and outputs and the control outputs of the switching elements of the rth row of the first matrix (p 1, N) are connected respectively to w With the information input-output and the input of the r-th block of the interface matching of the first group, the outputs of the matching blocks of the interfaces of the first group and the inputs of the matching blocks - the interfaces of the second group, respectively, form the groups of control outputs and inputs of the device, the tuning inputs of the switching elements of the first and second groups are connected to device setup input, characterized in that, in order to reduce the device reconfiguration time when organizing a multiplex mode of information exchange, an address meter, a group of memory blocks and a group of decoders, the counter reset input being connected to the device reset input, the content increase input address counter - with a setting input, the information output of the address counter is connected to the address inputs of the group memory blocks, the information outputs of which are connected, to the inputs of the corresponding group decoders, the address input of the switching element r-th. row and j-ro the first matrix of the first matrix is connected to the jth output of the rth decoder of the group, the address input of the switching element of the 1st row and the 1st column of the second matrix is connected to the jth output (N + p-ro of the decoder of the group . 2. The device according to p. 1, from l and more often, so that; the switching element contains the first and second elements I and Bus driver, the first and second information inputs-outputs of which form respectively the first and second information inputs and outputs of the switching element, the first input of the first element And is the address input of the switching element, the configuration input is connected to the second input of the first Element And, the output of which is connected to the sample input of the bus driver and the first input of the second element And, the second input of which is connected to the id of the input direction of the bus driver and form the control the input of the switching element, the output of the second element And forms control output of the switching element. FIG. 2 AT 9 i Ts . # -, S0