SU1635188A1 - Device for interfacing a computer to its peripherals - Google Patents

Abstract

The invention relates to computing and can be used in the construction of high-performance information and computing and measuring systems based on computers and peripheral systems. The aim of the invention is to expand the functionality of the device by providing work with various types of computer interfaces and in the conditions of multi-machine complexes with advanced control of the peripheral system. The device comprises a computer communication unit 1, a communication unit 2 with a peripheral system and an additional communication unit 3 with a peripheral system, an interface switching unit 7, a decoder 8, a unit for forming constants, a unit 10 for storing constants, a unit 11 for microprogram control, the register 12, the priority block 13, the switching load block 14, the mode setting unit 15, the bus and the communication line between the device blocks. 2 hp f-ly, 12 ill. with (S (L with

Description

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The invention relates to computing technology and can be used in the construction of high-performance information-computing and measuring and measuring complexes based on computers and peripheral systems.

The aim of the invention is to expand the functionality of the device by providing work with various types of computer interfaces and under conditions of multi-machine complexes with general control of the peripheral system.

FIG. Figure 1 shows a block diagram of a device for interfacing a computer with a peripheral system; Fig. 2 is a block diagram of a communication unit with a peripheral system; in fig. 3 is a diagram of an interface switching unit; in fig. 4 is a diagram of a unit for forming constants; in fig. 5 is a schematic of a storage unit for constants; in fig. 6 shows a block diagram of a firmware control unit; in fig. 7 is a block diagram of a priority block; in fig. B - block diagram of switched loads; in fig. 9 - 12 - diagrams of the device operation algorithm.

The device contains (Fig. 1) a computer communication unit 1, a communication unit 2 with a peripheral system and an additional communication unit 3 with a peripheral system, the main inputs-outputs 4, 5 and 6 of which are device-outputs of the device and are connected respectively to the main line of the computer interface, the main line and the additional line of interfaces, the decoder 8, the constants forming unit 9, the constants storing unit 10, the microprogram control unit 11 register 12, the priority block 13, the switching loads block 14, the mode setting bus and line 16 -34 st Zi between the units of the device.

Communication unit 1 includes a set of receiver-transmitters of computer interface trunk signals. The first input-output unit 1 is used to transmit control and synchronization signals. When a device is connected to a computer mainline with separate data buses and addresses, the second and third inputs / outputs of the computer communication unit 1 are used to transmit data and addresses on lines 16 and 17. When connected to an interLace computer mainline

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bus address and data of the third input-output unit 1 is not used.

The communication unit 2 with the peripheral system (Fig. 2) is intended for transmitting and receiving data signals, synchronization and states transmitted via the corresponding lines of the main trunk 5 of the interface of the peripheral system, and contains groups of elements AND 35-39, register 40, decoder 41, transmitter amplifiers 42 and receiver amplifiers 43. Register 40 is configured with a multiplexer at the input and provides storage for a command of the peripheral system recorded from two voltage sources - via lines 17 or 30.

The additional unit 3 of communication with the peripheral system contains a set of amplifiers of receivers and transmitters of signals transmitted through the lines of the additional inter- nal trunk of the peripheral system.

The interface switching unit 7 (FIG. 3) contains data registers 44 and 45 and addresses, a counter 46 and multiplexers 47-50. The multiplexers 47-50 and the communication structure in block 7 provide for register 44 the recording and reading of information on lines 16 and 13, for register 45 — writing from lines; 16 and read on line 17, for counter 46, write from lines 18 and read on lines 16-19.

The constant formation unit 9 (Fig. 4) contains a group 51 of three-way multiplexers and a decoder 52. The multiplexers of group 51 commute to each of the bits of the lines 18 or the state of the corresponding bits of the lines 19 or the constants corresponding to the logical values of O and 1 .

The storage block 10 of constants (Fig. 5) contains a ruler of registers 53, blocks of input and output multiplexers 54-56, providing for each of registers 53 the ability to write and read to two I / O connections connected to lines 18 and 30.

Microprogram control unit 11 (Fig. 6) contains a generator 57 for generating clock pulses, a condition register 50, a microcommand address generation unit 59, a microcommand address register 60, pa-.

There are 61 micro-instructions and a register of 62 micro-instructions.

Unit 13 priority (Fig. 7) contains the switch 63 requests, groups 64 and 65 of the elements And the priority encoder 66.

The switching load unit 14 (Fig. 8) contains a set of series-connected diodes VD and resistors R. The anodes of all the diodes are combined and constitute the enable input of block 14 connected by line 34 with the output of the mode setting unit 15. Terminals of the resistors are connected to the lines of the main 4 and additional 5 lines of the interface of the peripheral system.

With the help of the mode setting unit 15, a manual setting of the characteristics of one of the four possible modes of operation of the device, which is a combination of the choice of the type of computer interface, is made - with combined or separate address and data buses, and the mode of the primary or secondary controller of the peripheral system. In the firmware control unit 11, mode indicia are transmitted along lines 33 as two logical signals. In the case of the mode of the main controller of the peripheral system in block 15, the line 34 is connected to the voltage level of +5 V, the diodes are opened and the resistors are electrically connected to the lines of the lines 5 and 6, acting as load resistances. When an additional peripheral system controller mode is set, ground level is set on line 34, diodes are closed, and unit 14 resistors are electrically disconnected from lines 5 and 6.

The operation of the device is controlled by the firmware control unit 11 as follows.

Depending on the address code of the current microcommand stored in register 60, and the condition code in register 58, block 59 generates the address of the next microcommand, which is entered into register 60 by the pulse generator 57. This process is repeated for each generator clock 57. Thus, the combination of blocks 57-60 forms a firmware automaton that performs transitions according to states — adress

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the microcommands themselves, with the frequency of the generator signals 57. Block 59 is a permanent memory device (ROM), or, to reduce the memory size, a combination of ROM and a programmable logic array (PLA) connected in parallel to the outputs. The bits of the current microcommand address and conditions are used by block 59 as the input memory address for which the address of the next microcommand is stored. In block 61, which represents a conventional ROM, the current address of the microcommand is assigned a set of control signals — the microcommand itself, which, after sampling from the memory block 61, is recorded by the generator 57 into the register 62. A feature of the proposed device is the complete microprogrammability of all controls. signals, including computer interface and peripheral control signals.

The device can perform the following basic operations:

setting the initial state of the device blocks according to a reset signal in the computer interface;

program exchange of information between the computer and the internal addressable device registers;

software exchange of information between the computer and devices of the interfaced peripheral system under the control of the computer processor;

the exchange of information between the computer memory and devices of the interfaced peripheral system without the participation of the processor via the direct access channel;

interrupting the computer processor program on requests from devices of the interfaced peripheral system and internal requests from the interface device.

According to the reset or preparation signal in the computer interface, regardless of the address of the current microcommand, unit 11 proceeds to the firmware of the initial reset of the device (Fig. 9). It consists in sequential enumeration of the addresses of the register line 53 in block 10, forming for each of them by block 9 a constant of the initial state and writing it into block 10. This procedure is repeated as long as it holds

with a reset signal in the computer interface. Upon completion of the reset operation, as well as after performing all other operations, unit 11 goes to the initial state and starts performing initial polling cycles from the computer and the state of the control registers stored in block 10 in order to check the launch conditions of the direct channel. access and interrupt. A poll of the control registers in the initial cycle is introduced to simplify the implementation of block 11 of the firmware control by eliminating the need for microinterruptions.

Programming of the operation of the device from the computer side is carried out by means of program calls to the following registers from the computer side that make up the register line 53 of the block 10: the control and status register (RUS); Register of masks and requests (RMZ); high byte register (RSB); register access control direct access channel (RUK); the peripheral system command register (RC); register address memory (RAP); register of the word count (RCC).

The GB is intended for storing the operation code of the peripheral system, which is performed when it is accessed programmatically, the resolution bits of the interrupt, the general interrupt request from the device, the responses of the peripheral system devices during program accesses to them.

The DMS is used to mask the requests of the peripheral system in order to dynamically redistribute their priorities, as well as to read bits indicating the presence of interrupt requests from the devices of the peripheral system.

The SSB is used to negotiate the data width transmitted in software mode between the interfaces of the computer and the peripheral system. For example, the KANAK - 24 system's size, the majority of computers - 16 RSBs, is also used to temporarily store the CAMAC data start byte.

The ARM is intended for storing control bits and the state of the direct access channel: channel start, launch mode (upon request from a fixed peripheral device).

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themes, either immediately after setting the start-up bit), resolution of the interruption after the end of the channel operation, the flow of work on the computer interface (monopoly, with the capture of the computer interface for transmitting the entire information array, or multiplexed, with the release of the computer interface after each data word ), indications of the end of the channel operation, indications of the responses of the peripheral system devices when operating in the direct memory access mode, error indications during the direct access channel operation (time-out when accessing the computer interface, repolnenie memory address) register

The RC is used to store the command of the peripheral system that is executed when the channel is accessed directly.

ATM is used to store the address of the RAM, which is accessed via the computer interface during the operation of the direct access channel. After each access, the contents of the RAP is modified to indicate the address of the next element of the information array. Before starting the operation of the direct access channel, the initial address of the data array in the computer RAM is programmatically loaded into the ATM.

The PCC is used to count the number of data words transmitted by the direct access channel. Before starting the operation of the direct access channel, an additional code of the size of the data array is loaded into the PCC, which must be transmitted by the direct access channel. After the transmission of each data word, the content of the PCC is increased by 1, the normal termination of the channel is performed after the transfer of the entire specified data array, which is indicated by the PCC overflow.

When the device is connected to a computer interface with separate data buses and addresses, the first output of block 7, connected to lines 17, is in the initial state blocked. The address from the computer, received by block 1 and transmitted by it on line 17, is constantly analyzed by the decoder 8. When the address / address corresponding to the addressed registers of the interface device, or peripheral system devices,

a DND signal is generated, polled by block 11. In the case of connecting the device to a computer interface with a combined address and data bus, the third output-output of block 1 connected to lines 17 is blocked. Addresses, like data, are transmitted from block 1 via lines 16 and They are constantly tracked in the register 45 of block 7 and then through the open first output of block 7 are transmitted along lines 17 to the decoder 8. When the decoder 8 is triggered, the address is fixed in register 45.

Software references to computer-addressed registers of the interface device are made as follows (Fig. 10). When performing a write operation on signals in lines 20 from block 11, data received by block 1 is recorded in lines 16 through multiplexer 47 into register 44 of block 7, and then through multiplexer 49 transmitted through lines 18 to block 10. Block 11 generates the register address in block 10 and the write signal, as a result, data from lines 18 are written to the corresponding register of block 53 of block 10. Simultaneously block 11 generates a synchronization response signal transmitted through lines 21 through block 1 to main line 4 of the computer interface to complete the operation . Upon completion of the asynchronous cycle, the control unit in block 11 is transferred to the initial state via trunk 4 of the computer interface. During the read operation of the addressable register from the computer side, after starting up, block 11 generates the address of the required register in lines 24, and the read signal and data from the register of block 10 are transmitted on line 18. In block 7, under the control of signals from block 11, this data is recorded through multiplexer 47 register 44, and then through multiplexer 43, lines 16 and block 1 are translated into data lines of the backbone 4 of the computer interface. Then, by transmitting the response synchronization signal to the computer, the operation over the computer interface and in the interface itself ends.

When software is accessed from a computer to devices of a peripheral system, the command executed at the interface of the peripheral system is formed / as follows. Device address

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The peripheral system, consisting of the module number and sub address, is transmitted directly from the address lines of the computer interface, and the function code is selected from the ENG. The sequence of actions is as follows (11). After the operation of the decoder 8 at the address corresponding to the external device of the peripheral system, control of the interface of the peripheral system is performed, for which a request signal is sent to trunk 6. If there is no moment at the moment of a higher priority device requiring control of the interface of the peripheral system, this signal returns to the interface device via the trunk line 6 as an access ramp signal that comes from block 3 via line 26 to block 11, then from block 11, line 24, block 10 receives a command to read the switch over the line 30. The code 5 bits of the function RUS together with the address bits of the device of the peripheral system on line 17 are written through the input multiplexer into register 40 of block 2. It is located on line 18 and is recorded in the counter 46 of block 7. When performing a data read operation in the computer interface, after that, the command execution cycle is started in the interface of the peripheral system. If the interface device operates in the mode of the main controller of the peripheral system, the command of the peripheral system from the register 49 enters the corresponding lines of the highway 5 through a group of elements. Both 39 and the open decoder 41. If the interface operates in an additional controller mode, its decoder 41 is blocked and the module number is transmitted via lines 31 from block 2 to block 3 and further along trunk lines 6 to a similar device operating in main mode The controller of the peripheral system, where it is received by its own block 3, is transmitted via line 31 to block 2, is decrypted by the open decoder 41, and is transmitted to the corresponding lines of the highway 5. The rest of the actions are the same in both cases. Unit 11 generates synchronization signals of the peripheral system, transmitting them via lines 25 through the transmitters 42 of unit 2 in the trunk line 5. After working out

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The command of the peripheral system data and responses from the trunk lines 5 are received through groups of elements 36 and 38 and receivers 43 on the internal lines of the device 18, 30 and 25. On lines 30, the most important data bow is received, for its fixation in block 10 along the line m 24 a command is issued to write data from lines 30 with RSB. The remaining 16 bits of data through lines 18 enter block 7, where they are fixed in register 44 through multiplexer 47. The values of the responses of the device of the peripheral system are fixed in block 11 by a microprogram branch. To record their values in the ENG, in block 10, the contents of counter 46 (the old contents of RUS) through line 19 are output to block 9, which, depending on the address of the current microcommand (one of four), generates the required value of PS bits at the output. The remaining bits of the ENG block 9 are transmitted unchanged. The data from block 9 through lines 18 is then recorded by command from block 11 in block 10 in the ENG. Next, the data from register 44 through multiplexer 48, lines 16 and block 1 are transmitted to the data lines of trunk 4 of the computer interface. After the block 11 issues a response synchronization signal to the backbone 4 of the computer interface, the operation ends.

When programmatically writing data to a peripheral system device, data from a computer is recorded in the register 24 of block 7 and then transmitted through the multiplexer 49 and line 18 to block 2. Simultaneously, on the line 30 from block 10, the RSB data is read. When starting operation on trunk 5, data from lines 18 and 30 through groups of elements 35 and 37 of block 2 are transmitted to the corresponding lines of highway 5. The rest of the actions, including fixing the value of the responses of the device of the peripheral system to the radar and issuing a synchronization response signal to trunk 4 computer interface, are similar to those described

The execution of a group of control operations addressed to a peripheral system device in which the data lines of the highway 5 are not used as described above, depending on the type of read or write operation in the computer interface.

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The launch of direct access operations whose execution algorithm is shown in FIG. 12, is performed from the initial cycle, if the channel start condition is satisfied — the channel start bit is set in the hand transmitter and either there is a request from the selected device of the peripheral system, or the hand start switch is set in the hand transmitter. The selection of the request is made using the switch 63 of the priority block 13 when the interface device is switched on to the information processing system. After starting the operation, the device acquires a computer interface for direct access to the memory and the interface of the peripheral system. The capture of the computer interface is carried out by the firmware unit 1 in accordance with the requirements of the specific computer. For example, when connected to a computer with an interface, BUS 7, block 1 1 exposes a direct access request signal to trunk 4, after receiving a direct access permission signal, exposes a confirmation signal, clears the request, and after releasing the computer interface, sets its own signal Zan that. The operation of capturing the interface of the peripheral system is described above. Next, from block 10 on line 20, the contents of the RC are selected and recorded in register 40 of block 2 and register 12. Block 11 analyzes the type of operation of the RC — read or write. When reading is performed on line 18 from block 10, the contents of the RAL are read, which are loaded into the counter 46 of block 7, and the command execution cycle is started via the interface of the peripheral system. After the data appears on the lines of highway 5, they are transmitted through a group of elements 36 of block 2 and lines 18 to block 7, where they are entered into register 44 through multiplexer 47. Then, a data recording cycle is performed on trunk 4 of the computer interface. If the address and data buses in trunk 4 of the computer interface are separated, the address and data from block 7 through block 1 to the corresponding lines of trunk 4 are transmitted in parallel, respectively, from counter 46, multiplexer 50, line 17 and from register 44, multiplexer 48, line 16, If the address bus and the data in the computer interface are combined, first from the counter 46 through the multiplexer 48 on line 16 and then through block 1 to the trunk 4 the address is output, and then data is also transmitted from register 44. When the recording cycle in the computer interface 4 ends and the synchronization response signal is received by the block 11, the contents of the counter 46 modifies the counting pulses from block 11 via the lines and then is recorded via multiplexer 49 and line 18 to block 10 at the RAP address. This analyzes the overflow signal of the counter 48 transmitted to block 11 via the output line 20, which is fixed in block 11 by a branch of the microprogram. Then, using the counter 46 of block 7, the content of the PCC stored in block 10 is modified. The PCC overflow is also recorded in block 11. If the counter has not overflowed, the contents of the control panel are read from line 10 on line 30, then the register 12 is recorded. 11 analyzes the bit state of the RUC mode of operation along the mainline of the computer interface. With monopoly mode, not giving

the contents of the switchgear is read, the request bit is set with the help of block 9 in the nom, and then it returns to block 10. In addition, the block by block 13 blocks the operation of the priority block 66 to fix the interrupt vector.

When a direct access channel performs a write type operation on the interface of the peripheral system, after the capture operations, information from the main memory cell is read through the main line 4 of the computer interface. For this, from block 10 to counter 46 of block 7, the contents of the RLP are recorded, which are then transmitted to the address bus, either single or combined, bus 4 of the computer interface — the lannies from the memory cell are received by block 1 and through lines 16 and multiplexer 47 are written to register 44 block 7. Then this data is output on line 18 and the write command is executed at the interface of the peripheral system, in which the data of lines 18 through the group of elements AND

control interface of the computer, the device 30 35 block 2 are transmitted in the data line

enters the standby mode, in which the condition of starting the channel is analyzed, after the occurrence of which the cycle of transmitting information and modifying the contents of the registers is repeated. During multiplex operation, the device frees the interfaces of the computer and the peripheral system and returns to the initial state. During the next channel activation cycle, the operations of capturing the interfaces of the computer and the peripheral system are performed again. In case of overflow, when modifying the contents of the RAP or PCC from block 10, the counter 46 of block 7 records the contents of the KNC, which is transmitted to block 9, which is activated by signals from block 11. Depending on the branch of the firmware being executed, the output of block 9 is formed A new KEY content, in which the channel trigger is reset, sets the channel termination bit and, if necessary, the RAP overflow error. If in the ARM, the contents of which at this moment is recorded in register 12, the interrupt resolution resolution from the channel is set, from block 10 to counter 46 of block 7

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The records of the magistrate 5. The remaining actions in the device, including the modification of the contents of the RAP, PCC, RUK, RUS registers, are performed in the same way as described.

The procedure of interrupting the computer processor program from the interface device is performed as follows. The contents of the control unit are analyzed in the initial cycle, which is written from block 10 through lines 30 to register 120. Block 11 checks the status of the permit enable switch, which prohibits any interrupts from the device, in case of its reset. If the interrupt enable is set, the interrupt request bit is checked and, if it is set, the computer interrupts the process on trunk 4. If the interrupt request is cleared, as in the case that the interrupt is not enabled, the contents of the PMR are read into register 12 from block 10. Mask bits on lines 28 are transmitted to block 13, where bitwise the group of elements And 64 logically multiplies to requests from one hundred devices of the peripheral system, grouped with the help of switch 63 when switching on information

measuring system. Next, the priority encoder 66 allocates the highest priority non-masked request, generates its binary code and adds fixed base bits to form the interrupt vector. In addition, priority encoder 66 performs a logical addition of unmasked requests to form a general request signal, which is transmitted via line 20 to block 11 for analysis. At the same time, the requests from block 13, from the output of the switch 66 requests, the group of elements 65 and line 30 are written to the byte of the RMZ requests in block 10. When programmatically accessing the RMZ, they can be read into the computer. If the total request signal is set to 1 when the interrupt resolution is cleared, the general interrupt request bit is set to the ENG, for which its contents from block 10 is read into block 7, and then through block 9 with the substituted request bit returned to its place in block 10. If sigv

The total request or the corresponding bit of the control indicator has a value of 1 pi when the interrupt resolution is set, block 11 generates an interrupt signal to trunk 4 of the computer interface and then, in accordance with the specified interface type, the computer performs the interrupt procedure on trunk 4. For example, when the device is connected to the interface TOTAL BUS, further, after the device receives the interrupt enable signal, it removes the request and issues a confirmation signal. After the release of the computer interface by the current setting unit, block 11 exposes BUSY and INTERRUPT signals to trunk 4.

35 is connected with the peripheral system, the second output of the mode setting unit is connected to the third input of the logic conditions of the microprogram control unit, the second and third outputs of which are connected to the control inputs of the constants forming unit and the storage unit of the constants connected to the second input, respectively. and also from block 66 and line 16 - 45 home - by the output of the communication block with the periphery-interrupt vector. After being received by the rush system, the information in the synchronization signal is interrupted, the interrupt procedure is completed and block 11 returns to the initial cycle, and to prevent repeated interruptions for the same reason, the interrupt enable signal is reset to the control unit 10 RU.

Claims (1)

1. A device for interfacing a computer with a peripheral system, comprising five 0 a computer communication unit, a d-flick peripheral system, a decoder, a register and a priority priority connected to the first input-output of the microprogrammed control unit, the second and third inputs-outputs of which are connected to the first inputs-outputs of the corresponding unit the computer and the communication unit with the peripheral system, the first input of the logic conditions of the firmware control unit is connected to the output of the decoder, and the first output is connected to the control input of the register, the output of which is connected to, the resolution input of the priority unit and the second input of the logic conditions of the firmware control block, characterized in that, in order to expand the functionality by providing work with various types of computer interfaces and in conditions of multi-machine complexes with general control of the peripheral system, contains an interface switching unit, a constants formation unit, a constants storage unit, an additional communication unit with a peripheral system, a switched loads unit and a mode setting unit, the first output of which is connected to the input of the switched loads block connected by the outputs to the main inputs / outputs of the blocks 5 is connected with the peripheral system, the second output of the mode setting unit is connected to the third input of the logic conditions of the microprogram control unit, the second and third outputs of which are connected to the control inputs of the constant shaping unit and the storage unit of the constants connected to the second input, respectively. 0 5th house - output of the communication unit with the peripheral system, information input of the register and output of information about the requests of the priority unit, the output of the interrupt vector of which is connected to the second input-output of the communication unit with the computer and the first input-output of the interface switching unit connected the second input-output with the output of the block forming constants, the second information input-output of the storage unit of the constants and the third input-output of the communication unit with the peripheral system, with the first information output of the unit switching about „G 51 18 23 52 J FM.4 FIG. 7 FIG. five 6 VS 2 ... $ VI - "- / (line nams / gap 5 and 6 Fig.8 initial state Јс / пі .m (PS / xhpee.f2 there is Not ) pei.1Z Bt-ioiPH} pet.nt ffJl.t3 fAlOfPM3) ) att.1Z | fft.f3-fJt.) Hem Hem LRSCH uni  edura lreryba-zvn  SUЈ% S ™ JtMt / ct kona an / p- WVCWA troto value RUS, flyx 9 Is eating Sha UC / rjpoOOflSOs memory Reading Address BLU 6 / i. (regM) 6k1, Signal omS. si chronyatsatsts of the computer I The address is the 6th Data & TfpnMj-atn signal o / lb. simhranization computer FIG. YU , 3x8at LAN interface . Bl. Yu (rus) - ate. T (sch. 45) Team - l 2fpee. 39) Khomano-ps Cycle Magis / Prali 5 Data No. 2 t & Ureg. 44 blocgs Branching lo o / lde / am Jas t t i Formation of coddld + DSCR / (pe2, M) - fal- + Mff3 V Sognal. sinurom Overlap one Data: $ l. 7- + 6 / L2 6Ji10 (PC6) + ffA2 Cycle Backbone 5 O / p6lenuye / yus / p6et0 # hp    g Formation of xoffa ff / d-faiofpyc) Signal Otsev / pnu synchronization 9v # FIG. eleven ZachM / pm / LersheyosablMdl Do sh / perfeisa PS one 16l. 10 (RC) ffji. 2.6 liters 12 6l. U (RUK) bl. 7 (SCh6) cycle highway 5. This- $ A bl 7 (reg. 44) Rormir.koda6l .. 10 / RC there is b / y. (RAL). 7fCVM) recording data / x in computer ± +2 (C44S) fa. W (PAff) de / p6 lentzoleler / u / 1 # emu f / em 6l U (RCC) bl. 7 / CV VM +1 (C4V6) frr.10 (PCC) 9et8 leneler (/ yomem bl. U (RAP) bl. 7 {MF / b) Bottom-5l. . 7 {regM) ± 6l. 10 (Py / (hfa. 7fC9.45) MAGs cycle / s / prom 5 Given: & l .2 6Sta8Leloo 6e / gyun / s ± Wo Jljl Formation of the hoss $ l..Yu (Ruh) there is Error # ate 5l. 10 {Rap) bl.7 (with “BH) i d, 7 / L YURUM + OL. 7fCV V6i    chroism - UL} 0 (RUU ЈС / 77А L.L.Y. (RUS) h0l. 7fCVJfЈ) Jmww #eat FIG. 12