SU525953A1 - A multiprocessor computing system with variable configuration - Google Patents

Description

one

The invention relates to computing and, in particular, to the design of multiprogram MHoronfJOueccopHbix systems operating in real time.

In a real-time multi-program calculator, the B1x systems operating on a real-time basis, the only scrupulous problem is scheduling, i.e. the choice for execution on the processors of the most important programs from the queue of programs waiting to be executed.

The solution of this problem by software methods for such systems is unsatisfactory, because of the large amount of time spent on dispatching functions. The required level of performance in real-time systems can be achieved by assigning Dispatch functions to the equipment.

; In a computer system with a variable Configuration, the hardware that is dispatched to the function is superimposed on the additional requirement that the processors that are disconnected from the system

during reconfiguration, should be excluded from the set of equipment involved; in the dispatching of programs. If during reconfiguration the system is divided into several independent subsystems, then each subsystem must have its own npow. dispatching department on the equipment 1S, BXoJ above 1 only in this subsystem. If, on the other hand, a high-powered system must also have a high survivability, then the hardware, which performs the dispatching function, must be decentralized, that is, distributed among the processors. Otherwise, the failure of a single device, namely the one that performs dispatch functions, leads to the failure of the entire system.

Known multiprocessor computing systems with variable configuration, containing processors and memory devices, the first output of each of the processors connected to the corresponding input) gte -flOi (groups of inputs of other processors, the second output of each of the processors connected to the corresponding input of the second group of inputs of other processors , the third output of each of the processors is connected with the corresponding input of the third group of inputs of the other processors, the fourth output of each of the processors of the connections with the corresponding The input of the first group of inputs of each of the devices is naMSTTH, the fifth output of each of the processors is connected to the corresponding input of the second group of inputs of each of the memory devices, the first output of each of the memory devices is connected to the corresponding input of the fourth group of inputs of each of the processors However, this multiprocessor system is characterized by the complexity of organizing a multiprogramming mode of operation with changing configuration and a large additional investment of time. The purpose of the invention is to increase the speed of operation and reliability of the system. The proposed multiprocessor computer system with a changeable configuration differs from the known ones in that each processor contains an operation block, a configuration register, a redundant processor processor number register, a current priority register, a software queue fill register, a lock trigger, a second selection circuit, a nepByiq, and a third selection circuit. Comparison diagrams, first, second, third and fourth groups of elements AND, element AND, first, second and third elements OR, and the first output of the operating unit is connected to the input p The configuration register, the first group of outputs of which is connected to the first inputs of the corresponding elements AND of the first group of elements AND, the second group of outputs connected to the first inputs of the corresponding elements AND the second, | Third and fourth groups of elements AND, BT & The first inputs of the elements of the first, second, third, and fourth groups are connected to the corresponding inputs of the fourth, first, second, and third groups of inputs of the processor, the outputs of the first group of elements of And are connected to the first inputs of the corresponding comparison circuits of the group of comparison schemes, the second inputs of which are Dinoi soybeans with the first processor output, with the output of the position register, the process number of the processor, with the first inputs of the operating module and the first comparison circuit, and the outputs -. connected to the inputs of the first element OR The output of this element is connected to the second input of the operating unit, the second output of which is connected to the input of the program queue filling register, the output of which is connected to the input of the first selection circuit and its output is connected to the first input of the second comparison circuit, the second input of which is connected with the second processor output, with the first input of the third circuit comparing with the output of the current priority. The first output by the comparison circuit is connected to the third input of the operating system, and the second output is connected to the one input of the locking rigger, the zero output of which is connected to the first section of the I element, the output of which is connected to the fourth exit the block, and its third speed of the aelean in the queue is connected to the third output of the pre-processor and the first input of the second IDN element, the other inputs of which are connected to the outputs of the fourth group of AND elements, and the output is connected to the zero input of the trigger block ki, outputs of elements AND of the third group are connected to the inputs of the second selection circuit, the output of which is connected to the second input of the third comparison circuit, the first output of which is connected to the first input of the third OR element, and the second output is connected to the first input of the third selection circuit, others the inputs of which are connected to the outputs of elements AND of the second group, and the output is connected to the second input of the first comparison circuit, the output of which is connected to the second input of the third OR element, the output of which is connected to the second input of the AND, fourth, fifth, sixth and The seventh YO moves of the operating unit are connected respectively to the fourth output of the processor, the privileged mode bus from the fifth output of the processor, to the input of the register of the position number of the processor and to the input of the register of the current priority. Each memory device contains a memory block, a sampling control block, a block of step-by-step operations, a radio configuration register, a position number register, a logical number register, the first and second comparison cxeMbj, the first and second priority switches, the first and second groups of electronic & And, the group of elements is NOT, and the first output of the system operative block is connected to the inputs of the logical number register and the configuration register, the outputs of which are connected to the nepBbihysi-i inputs of the corresponding elements of the first and second groups, the second inputs of which are connected with the corresponding inputs of the first rpjTini.s input of the memory device, the third inputs of the first group of elements AND directly, and the second group of elements AND through the elements are NOT connected to the corresponding inputs of the second group of inputs of the memory device, the outputs of the first g uppy AND elements are connected to first inputs of the first comparator circuit OUTPUT. which soy with the inputs of the first priority switchj whose output is connected to the input of the system operations block, the second output of which is connected to the input of the position number register, the output of which is connected to the second input of the first comparison circuit, the outputs of the second group of elements And are connected to the first inputs the second comparison circuit, the second input of which is connected to the logic level and the outputs are connected to the inputs of the second priority switch, the output of which is connected to the input of the sampling control unit associated with the storage unit, the output of the sample control unit is connected by an information bus to the output memory device. The drawing shows a structural electrical circuit of a multiprocessor computing system with a variable configuration. The proposed multiprocessor computing system contains a processor 1, a memory module 2 (a memory device), an operation unit 3, a processor configuration register 4, a processor position register 5, a current priority register 6, a program queue register 7, the first circuit 8 selection (major number), loopback trigger 9, second selection circuit 10 (lower priority), third selection circuit 11 (minor number), comparison circuits 12-17 (group of comparison circuits 12), memory configuration register 18, position 19 register 19 memory measure, register 20 of logical memory number, first and second priority switches 21, 22, unit 23 system operations, unit 24 sampled, storage unit 25, groups 26-31 elements AND, element AND 32, elements OR 33- 3 a group of 36 items of NOT, an interrupt bus 37, a queue bus 38, a privileged mode bus 39, processor information buses 40, memory information pages 41, a list sampling bus 42. A multiprocessor computing system contains several processors 1 and several memory modules 2. Each processor has a register 5 of the position number of the processor (made, for example, on tumbler), which is set constant for the given computing system. All processors have different numbers. Each memory module 2 also has a register (19 position) memory numbers, which, in each module, is installed sequentially for a given computing system-j. All memory modules 2 have different positional numbers. Each memory module | 2 has a register 20 of a logical part number, the contents of which determine which processor module 1 is addressed to 1 which memory module 2 is addressed. The configuration of a multiprocessor system is determined by the contents of register 4 of the processor configuration and register 18 of the memory configuration. If all the bits of these registers are set to position I, then the system forms one complex, which includes all the processors 1 and all the memory modules a and 2. The communication between them for the exchange of information in this case is carried out as follows . Operational unit 3 of processor 1 excites. On processor information buses 40, the address of the memory cell being accessed is information that needs to be recorded at the specified address in the case of one- I recording radio, as well as the pos1 number of the position number 5 processor. At the same time, on the bus 39 of the privileged mode, there is no signal and output 6d1 of the group of 36 elements of the NOT memory modules 2 value. Signals from the information bus 40 of the oral process pass under the above conditions through the first group of 27 elements AND all memory modules 2 and are fed to the inputs of the second comparison circuits 17, which compare the high-order bits of the address with the contents of the register 20 of the logical memory number and in case of coincidence, the input is switched; information to the input of the second priority switch 22. The second priority switch 22 in the case of simultaneous access to the memory module 2 is set: processor 1 selects and switches information from one to its output from the inputs by positional priority. Block 24 of the first sample makes a call to the storage unit 25 according to the A. A. Cresu principle and commutes to the information buses. 41, the position number of the processor from the corresponding bits from the output of the second priority switch 22. Sits from the information buses of the module 41 pass through the first group of 28 elements AND processor 1 are fed to the inputs of the comparison circuits 12, where they are compared with the contents of the register 5 position: numbers gfotsessso1 a. Coincidence of numbers means that the memory module has received a request for a call from this processor 1 and has received the operation specified by the processor. In this case, in the case of a write operation, the comparison circuit 12 through the first one -,;; el; element OR 35 carries the signal into onepaiui. On-line unit 3, fixing the end of the communication session of the processor with the memory module 2. When performing a read operation, the module on MITI 2 excites on the informational 5 Haxj41 memory, in addition to the number of the processor number, also the read information from the specified memory cell 6k.k25. The comparison circuit 12, through the OR OR 35, commutes the information from the formatted IQ tires of the 41 ti into the operative block 3, ko-. Secondly: on one of the information buses 40 of the processor, it signals the module gmi mi 2 about the end of the communication session.

Multiprogramming work in this system is organized in a 15-way system; ,

i Operational system, post the program. | in memory, assigns .each program priority (possibly jijjHCBoeiiKe equally ".2th priority to several programs)., For,; .everything from the possible priority values, the operating system generates an order: programs, when part of the queues may be empty, if at the current moment there are no programs with the given priorities in the subject. For definit ... In a lazy non-empty program queue, the operating system records, in the facsimile memory cell (for example, in the module with “30 logical number”), the units in bits that correspond to empty.

I When performing gfogram; HY on the process - reg - 1 in reg. 6 of the current priority of the order is carried out - the priority of the program to be implemented. After the end of the race, the nporpaNSMb registrar. current pr.korkteta Gg. . Llsharat fa processors continuously compares the priorities: rsonsibles.} About the processors and the processors, the programmer has the same ik.k.ky lrkkt-kt, ktyvvtsy kanyidatom on interrupt. This processor checks if there are any queues in the sync pro-; Gram with a priority higher than the g that orf uses; if “there is such a gram, then the processor kk kiwW on a jerk interrupts the execution of the current program,” her queuing and queuing from the list of instructions for the jjj program with the highest priority.

The operation of the instrument at & tom Rrog is as follows.

When the current | |: yr - p «tmf G: an action block 3 is taken, with a priority & g in 6 6 of the current npjioji rreia. Ischrt-tm m regreggra current priority kvzhpog) processor comes across the group: O

and vtopyo scheme; . About choice

Elbmeite

(younger state) proxy processors .1., G

In Ks, the house where upoueccoj 3 is second .-. G, scheme 10 of the choice (junior priority) was implemented. There is no comparison of the current priorities of others. Cessors and commutes to you. Enter the code of the best from the current process: priorities. In case of equality of codes - akuzh; - prior - tags on input. the second IW of choice on its e-mail session: 1 h; code of compared current priorities. The code from the output of the second circuit 10 of the U5U system is not triggered to the input of the third compres son 13 comparison (priorities) for comparison with the contents of the register 6 of the current priority of the given processor. If soderm1 mine this register current1g5 prio. This processor code. It is processed by the second selection circuit 10, then a long processor with a caMbiM low priority and sets the Q2nd.adat interrupt. At this third, the 13s circuit produces a CBO &h; hi signal on the second output, which If the contents of register 6 of the processor’s current priority are greater than the code generated by the second circuit 10, then this processor is not; it is a candidate for interrupted and first to second outputs of the third circuit 13 If Ia Eai is the contents of register 6 of the current priority equal to the code of the next current priority, this means that two CPUs of the processor 1 are equipped with programs of the same prioritta, In this case, the candidate CPU for the Kelladpem (Toz.) scaler trap Kchi schemes 1 choice; -; (ml dshe numbers.) and Skemmay J-- srvvke;.; and ;, workiouiK vrn viv-log. 0 i-infJopa and with e / lam 13 cpaBHGHHS coagweg - ;; yno „

G1r. And this has come up to him on his own; 13 s: ravenki. is equal, and on its first wavelength, to develop a sappap, including a third choice scheme 1.1, on I B5 C. The ID of which is p.fopyio d-ruppa 29 e-hgv cops AND sTopTjTiaeT {1x: fm; -1c from exits. of registers 5 posionionl-l: numbers of ggroesors J., Code according to the fused tube from 11y;: one of the third choice scheme 11 nc-cTjTJaeT for all first cxfif fbi C; advance 14, those with | Awarded with Sodr; shm POJ-HCIT "5 poidogpogo numbers piiogt) np-Hiec-sora .1,

Claims (1)

If the register number 5 of poksh10g1g1 of the last number is less than the code of the code m.;) "L.: | Gf; h YAO.EKP.YO1SHOGO number, then cpfiir-. kenk 11 ibipfmaTbinanr of this-pl, which the Third Earthman 1-1 / 1 and 3 enters the element vlode I 32. 11nn this, they sat down with a trigger. (9) 6jiOKHjDOBiai (tearing) is in the position O, then the element And 32 excites the signal Sending: not 42 list selection, connected to the input of the operation unit 3. Operational unit 3 selects from the M.si to the register 7 of the gfogram queue transmission, the contents of the frunched ghost storing the pointers of empty program queues. Selection scheme 8 (senior number) selects from register 7 (filling out the pro- gramming queues of the senior number Ggryori. Program theta, located in the list of queues, and transmits this dimension to the input of the second comparison circuit 15 (priorities) compares it with the current priority of the current priority register 6 of 6, and if it contains the register of sixth priority lower than the priority code from the list of queues, the second comparison circuit 15 generates S1signap on the interrupt bus 37. In this case, processor 1 interrupts the execution of 1 It is currently programmed to it and enters it into the list of program queues 1 with the priority corresponding to the current priority register register 6. Then processor 1 selects the program with the highest priority from the list of queues and transfers its priority to the current priority register 6 and receives execution of this program1-.sh1. If the contents of register 6 are tec with; priority of a large priority code of the program “we have the highest priority of the queue, this means that in the program queue they have priority I lower than 5 hegrogram -program. In this case, the second comparison circuit 15 generates a skal, which sets the trigger of the blocking device into operation; to & lori ehajayet ope1lo; yy and 32. The trigger block22 9 is reset to put O when the processor 1 of the program is listed in the queue list. At the same time, processor 1 is generated on the W1SH 38 and entered into the queue, which is tia. input of own second element OR 34 l through the fourth gr. “bite And 31 elektekosis fa entrance of elements IL 34 other nprocessorosis 1o C YOU; SODB element I, G1.I 34 scgaa. to the input of the gauge - BLAH trigger bloch 9 ,, Iomenenez T 5nfv7ur tt11k scstemt / unst il ets regreg ir; tmn 4 kof rurgg: u; ppcess-. Sors and reg.13 13 Config. Installing regxgra 4 processor falsch config is made by oieryshukshlm blots 3 "Part of registers 4 registers of Lroyessor's key are disconnected from npoixec cords 1 memory modules; The processor configuration is used to exclude the processors 1 from the multiprogramme system of work. With siTOM, the second group of 29 e & meytov I serves to exclude the processor being disconnected from the comparison procedure with the third numbers, the third group of 30 I elements. to exclude from the procedure of comparison of current priorities and the fourth group of 31 elements And to exclude the procedural 1 from the reset procedure of KHpoBji 9 block triggers 9. Register 18 configures memory memory for disconnecting from memory modules 2 memory 15 is set by operadio, unit 3. one of the processors 1. In this case, the operation unit 3 generates a signal on the bus 39 of the privileged mode and in the memory modules 2 "the corresponding groups of 26 AND elements are hidden, and the group of 36 elements DOESN'T close the uppu 27 elements I. The privileged mode of operation modules RAM memory 2 is performed at POS1 Ziona number stored in register 19 pozishyunnogo number memory. At the same time, the high-order bits of the address through the first group of 26 elements And arrive at the input of circuits compared with 16, where they are compared with the soda of the register 19 of the positional memory number. In the RAM module, where these numbers coincide, the comparison circuit 16 transmits information to the ECOD of the priority memory. - switch 21, which in case of simultaneous access of several processors 1 selects and commutes to its output information from one source on the basis of individual priority, I Block 23 of system operations, respectively; From this interface, the memory controls the yo-i register in register 18 of the memory configuration and register 20 of the logical memory number. By changing the contents of register 4, the config file processor, register 18 of the memory configuration, and register 20 of the logical memory number, it is possible to disconnect the faulty processors 1 to modules 2 of the operative {PM} and in order to force individual modules | program programs, multiprocessor sub-Teivibin For example, you can organize two such iodies & t by setting up pairwise logical logic cameras of memory modules 2, unplugging from registers 18 configuration-J of memory i.Tpoiieccopbi of one subsystem 1-11 from operational modules memory 2 is another deist; vibi p disabling register; processor modules one; . processors of the other subsystem from the system and processors of one subsystem from the equipment of the multiprogram operation of the other subsystem. At the same time, the equipment automatically provides multi-program operation of each subsystem. A multiprocessing computing system with a variable configuration, containing processors and memory devices, wherein the first output of each of the processors is connected to the corresponding input of the first group of inputs of other processors, the second output of which the second processor is connected to the corresponding input of the second group of W-ods other processors, the third output of each of the processors is connected to the corresponding input of the third group of inputs of other processors, the fourth output of each of the processors is connected with the corresponding the input of the first group of inputs of each of the memory devices, the fifth output of each of the processors is connected to the corresponding input of the second group of inputs of each of the memory devices, the first output of each of the memory devices is connected to the corresponding input of the fourth group of inputs of each of the processors characterized by the fact that, in order to increase the speed and reliability of the system, each processor contains an operating unit, a register of the configuration {and, register of the positional number of the processor, {yugister of the current priority, register of lneni software) 1x turns, trigger block}, the first, second and third selection schemes, the group of comparison schemes, the first, second and third matching schemes, the first, second, third and fourth groups of elements And, element And, first, second and the third OR element, moreover, the first output of the operation unit is connected to the input of the configuration register, the first group of outputs of which is connected to the first. by the inputs of the corresponding elements AND of the first group of elements AND, the second group of the moves you connect to the first inputs of the corresponding elements AND of the second, third and fourth groups of elements AND, the second inputs of the elements I of the first, second, third and fourth points are connected to the corresponding inputs the fourth, first, second and third groups of processor inputs, the outputs of the first group of elements I are connected to the first inputs of the respective comparison circuits of the group of comparison circuits whose second inputs are connected to the first output of the quarrel, with the output of the register of the positional processor number, with the first inputs of the one block and the first comparison circuit, 5 53 --52S, - and the outputs - are connected to the inputs of the first OR element, the output of which is connected to the second input of the operation module. unit, the second output of which is connected to the input of the register of filling of software queues, the output of which is connected to the output unit, the first selection circuit j, the output of which is connected to the first input of the second comparison circuit, the second input which is connected to the second output of the processor comparison with the current priority register driver, the first output of the second control circuit is connected to the third input of the operating unit, and the second output is connected to the single input of the trigger trigger, the zero output of which is connected to the first output By the stroke of the element I, the output of which by the list selection bus is connected to the fourth input of the operation unit, the third output of which is connected to the third by the bus entry; the output of the processor and the first input of the second element OR, the other inputs of which are connected to the outputs of the fourth group of elements AND, and the output connected to the zero input of the blocking trigger, the outputs of the elements AND of the third group are connected to the inputs of the second selection circuit whose output is connected to the second input of the third circuit comparison, the first output of which is connected to the first input of the third element OR, and the second output is connected to the first input of the third selection circuit, the other inputs of which are connected to the outputs of the elements AND of the second group, and the output It is not connected with the second input of the first comparison, the output of which is connected to the second input of the third element OR, the output of which is connected to the second input of the element AND, the fourth, fifth, sixth and seventh outputs of the operation unit are connected respectively to the information bus with the fourth output processor, the privileged mode bus with the fifth processor output, with the register input of the processor's position number and the current priority register input, and each memory device contains a storage unit, | sampling control block, system block | operations, configuration register, position number register, logical number register, first and second comparison circuits, first and second priority switches, first and second groups of elements AND, group of elements NOT, and the first output of system operation block I is connected to inputs: dami of the register of the logical number and the register of the configuration, the outputs of which are connected to the first inputs of the corresponding elements AND the first and second, the second inputs of which are connected to the corresponding inputs of the first group of inputs of the memory device, t The first inputs of the first group of elements are And directly, and the second pear of the elements And through the elements are NOT connected to the corresponding inputs of the second pear of the memory device, the outputs of the first group of elements And are connected to the first steps of the first comparison circuit, you are connected to the inputs the first priority switch, the output of which is connected to the input of the system operation block, the second output of which is connected to the “register code of the position number, the output of which is connected to the input of the first comparison circuit, the outputs of the second group of elements I are connected to the first inputs of the second comparison circuit, the second input of which is connected to the output of the logical number register, and the outputs are connected to the inputs of the second priority 1M) input, which output is connected to the input of the block control of the sample associated with the memory unit, the output of the sample control unit is connected by an information bus to the output of the memory device.