SU1596339A1 - Computer to peripheral interface - Google Patents

Abstract

The invention relates to computing technology and can be used in the construction of information-measuring computer systems with a common bus and peripheral systems with direct addressing of device registers. The aim of the invention is to increase reliability due to hardware operational control of work. The device contains an exchange control unit, two decoders, two switches, a trunk acquisition node, a flip-flop trigger, a control register, an address selector, an address register, a number register, two OR elements, two I. And I. elements. f-ly, 6 ill.

Description

The invention relates to computing and can be applied when building information-measuring systems using a common bus computer and peripheral systems with direct addressing of device registers.

The purpose of the invention is to increase reliability by providing hardware operational control of work.

Figure 1 shows a block diagram of a device for conjugation; Figures 2 through 6 are diagrams of a first decoder, an exchange control unit, a control register, a second decoder, and a second switch, respectively.

The device contains (Fig. 1) a first decoder 1, a control register 2 for storing the peripheral subsystem number, interrupt enable signals and indications of the results of the peripheral system operations, the exchange control unit 3 controlling the exchange operations with the computer and the peripheral system, the first switch 4, switching the group of bits of the addresses of the common computer bus with the group of addresses of the device registers and the operation code of the peripheral system, and the switching is performed according to the conditions for obtaining the shortest computer programs, register 5 but | measure, specifying the number of the co-operating device, the yarn, the first gain block 6, connecting the device with the common bus of the computer, the second gain block 7, connecting the device with the common bus (trunk) of the peripheral system, the common bus 8 computers, common pipu (trunk) 9 of the peripheral system, node 10 of the highway capture, implementing the operation of capturing the common computer bus, address register 11, assignment range. addresses of the peripheral system, the second .coder 12, the second switch 13,

switching commutator, the state of the flip-flop trigger and the code specified by the register 5. numbers, with a group of data bits of the common computer bus, the elements OR 14 and 15, the elements 16 and 17, the flip-flop 18 and the address selector 19.

The first decoder 1 (FIG. 2) consists of a reference element 20 and a decoder 21.

The exchange control unit 3 is formed by (FIG. 3) elements AND 22-24, elements OR 25 and 26, delay elements 27 and 28, elements AND 29 and 30, element 31 and trigger 32.

Control register 2 contains (FIG. 4) output 33, switch 34, register 35, NOT element 36, IL 30 element and delay element 38.

The second descrambler 12 (figure 5) is made on the decoder 39.

The second switch 13 contains (6) elements AND 40-44, elements 45 and 46 and element AND-OR 47.

The common computer bus is a unified system of communications and signals between the processor, random access memory and interface devices with peripheral devices and systems. The communication between devices participating in a common bus operation is asynchronous. The trunk of the peripheral system is a unified system of communications and signals between the peripheral system and the control unit, the function of which implements the proposed device. A peripheral system can consist of one or more subsystems, each of which contains a group of devices. Each device can contain a group of addressable registers. In addition, several proposed interface devices can be connected to a common computer bus, each of which has its own peripheral system.

The interface device is intended to match the incompatible signals of the two interfaces. Most of the common bus signals are interpreted into the corresponding peripheral trunk signals.

The device works as follows.

The operation of the proposed device when performing input-output operations is similar to the work of the known. Consider the operation of the device in the distribution of address lines A (0) ... A (17) of a common computer bus, for example, in the following way: bits A (17) -A (12) indicate the beginning of the address range of the peripheral system connected with the device mates; bits A (11) -A (8) determine the address of the peripheral device Y (8,4,2,1); bits A (7) -A (4) determine the address of the device register P (8,4,2,1); bits A (3) -A (0) define four bits of the opcode F (8,4,2,1). The fifth bit of the operation code, which identifies the main type of operation (write or read), corresponds to the signal of the common computer bus operation.

With a received addressing system, the peripheral subsystem can contain up to 16 peripheral devices, each of which can have up to 16 registers.

Proceeding from the condition of minimum use of computer addresses, the own device interfaces for interfacing (with the number one) are addressed as follows: control register by Y (0), P (0); The control circuit for processing the requirements for Y (0), P (1), where Y (0) and P (0) denote the zero value of the bits of the device and register numbers. When organizing in one address range of a peripheral system, up to eight such interfaces can be connected to a common computer bus using the following addresses for their own: schemes: Y (0), Y (P-1), Y (0), Y (2P -1), where P is the number of the pairing device. Each of the connected peripheral subsystems uses 2K addresses (K 1024), since bits A (0) -A (11) determine the address of the register and the device and the operation code (the bit of the bit). The rest of the computer addresses are assigned to the addresses of the memory cells and the registers of the system peripheral devices. At the same time, from one to eight peripheral subsystems (but not more than eight to the computer) can be connected to each interface device, for which an appropriate number of bits is reserved in register 2 Dov for storing the number of the peripheral subsystem.

Claims (2)

The device exchanges data between the registers of devices of the peripheral system and the operative 5 memory of a computer controlled by a program using alarms. In accordance with the program, the time of data transfer is determined and initiates the first stage. The following information is set on the lines of the general computer bus: the write code, the address of the register line 2 is in accordance with the number of the interface device and the beginning code of the address range of the peripheral system, on the data lines the code corresponding to the number of the peripheral subsystem and signal no interrupt is allowed, after a fixed shutter speed the clock signal. Address selector 19 analyzes the address arriving through block 6 from the common bus 8 and responds if this address is in the address range of the peripheral system specified by register 11. This switches on switch A and receives the received address to the input of the first decoder 1 and 7 to the common bus 9. The address received from the switch 4 is decrypted according to the number of the interface device specified by register 5 in the decoder 1. The decoder 1 determines that the address belongs to the control register 2 and sends an enable signal to block 3 on the information of the computer with register 2. Then block 3 receives through block 6 of the general bus 8 a write operation code and a sync signal and sprinkles to register 2 a signal to write data from block 6 to the inputs of register 2. After writing data in register 2 block 3 generates a response sync signal and sprinkles it through block 6 into a common bus 8. The computer receives this sync signal, removes the synchronization signal, and then the data, addresses and control signals. After the clock is removed, the device removes the response clock; in this, the first stage of initiating an I / O operation is completed. As a result, register 2 stores the code of the number of the peripheral., Under the system and the signal of the resolution of the order. The computer then begins the second step of initiating an I / O operation, sending it through the device to one of the registers of the peripheral device control information to start it. For this, the computer places on the common bus line the address of the peripheral system, the code of the record, the address of the peripheral device and its register, as well as the corresponding four bits of the operation code, after a fixed delay a clock signal. The address selector 19 is activated and the switch 4 is turned on. The address is fed to the input of the decoder 1, which determines that the address refers to the addresses of the peripheral system and the signal of the loop start on the peripheral trunk, which sends to block 3. Block 3, having received a write code and a clock signal from the shared bus of the computer via block 6, initiates a peripheral trunk cycle, transmitting through the block 7 to the common bus 9 the number of the peripheral subsystem from register 2, the write code and the clock signal. P1 of the common bus 8 to the common bus 9 through blocks 7 and 6 directly along the data lines receives additional information for the peripheral device, and through the switch 4 - bits of the peripheral device number and register number. After the operation has been performed, the addressable peripheral subsystem sets the clock signal and the response signals, which are transmitted through block 7 to block 3 and register 2, respectively. Block 3 gates the reception of response signals to the corresponding bits of register 2, and then removes the information and clock signal, completing the operation on the trunk peripheral system. After the signals are removed, the peripheral subsystem removes the clock signal, after which the block 3 sends the response clock signal through the block 6 to the shared bus EBY and then finishes the operation on the common bus. This completes the second step of initiating an I / O operation at the peripheral device. The value of the response signal stored in register 2 can be read by the computer when accessing register 2 by reading. In this case, the contents of register 2, according to the signal from block 3, are fed through block 6 to the computer. Information about the state of the peripheral device, stored directly in the peripheral device register, can also be read by the computer when it is read into the peripheral system register. In this case, the obsessive register of the peripheral device when executing the cycle of the perimeter highway enters the data lines through blocks 7 and 6 directly into the computer. After initiating an I / O operation in the peripheral device, the computer continues the execution of the main program. Consider the procedure for transferring data to the device register of the peripheral system that is currently having a request. The request signal is decelerated from line 9: through block 7 to the input of the And 17 element. X1 a signal in the register 2 Enable interrupt is transmitted to the other input of the And 17 element, allowing the request signal iepes 17 to pass through. From the output of the element And 17, the request signal enters through the element OR 15 in the node, THEN captures the trunk. The appearance of the request signal starts the node 10, which, exchanging control signals with the computer through block 6, performs an operation; capturing the common bus and interrupting the current program. At that, the node 10 generates a signal for discharging the query word output, which is fed to the control input of the switch 13. From the output of the switch 13, the query word generated by the register 5 enters the common bus via block 6. As a result, the computer goes to the service program. This device pairing usually starts its program by searching for the cause of the interruption in the peripheral system: 1). case one common query line. For this, the computer initiates read operations from the peripheral system of the query word; The demand processing control circuit in accordance with the interface device number, and after a fixed delay of the synchronization signal, the address of the interrupt processing mode control circuit received from the common computer bus passes through switch A to the input of the decoder 1j which establishes its compliance with the address of the control circuit and sends block 3 is a signal on which a demand processing mode cycle begins on a peripheral highway. To do this, block 3 transmits through block 7 to trunk 9 signals of sampling all subsystems and a request reading signal, by which the control unit of each subsystem (or peripheral device), which stores the request signal, puts codes on the JJ line of trunk data 9 to identify the sources of requests in the subsystem . On the data lines, the query word of the system is thus established. Upon receiving clock signals from all subsystem control units, unit 3 sets the response clock signal, after receiving which the computer reads the query word from the main data lines through blocks 7 and 6. The computer terminates the operation on the common bus and block 3 on the peripheral system trunk. Then, the computer according to the program searches for the source of the request for processing the request, depending on the principle adopted in the peripheral system for identifying the sources of the requests. After the software determines the register number of the peripheral device requesting data for transmission, the computer organizes the operation of transferring the data word from this memory into this device register or receiving data from the register in the same way as described initiating procedure. nor an I / O operation. When a failure or malfunction occurs in the process of executing an I / O operation, the proposed device operates as follows. I. When initiating data exchange between registers. peripheral system devices and computer RAM under the control of the program the register address comes from the common computer bus Cher-3 block 6 and switch 4 to the input of the decoder 1. The following three types of signals can be generated at the output of the decoder, depending on the register address code: or a control register access signal 2 (to the interface device's own registers), or a peripheral trunk cycle start signal, or a request signal to the control circuit of the demand processing mode. All these signals arrive at block 3 to start it upon the arrival of a sync signal from the common bus of the computer to perform the exchange cycle. In addition, these signals simultaneously arrive at the OR 14 element, at the output of which a combined computer access signal is formed through this device for conjugating to the registers. From the output of the OR 14 element, the signal of the post element I 16 is turned on. Input to the second input of the second decoder 12 from block 6, information is received about issuing to the common computer bus a response sync signal by some device (other interface device, random access memory or system memory). peripheral devices) connected to a common bus. The first input of the second decoder 12 receives a response sync signal generated by block 3 after the end of the peripheral trunk cycle or access to its own registers and circuits. Since the communication between devices connected to the common bus operation is asynchronous, faults or failures) to the registers of the peripheral system connected via this interface device (or to its own circuits or device registers) and to the registers of system peripheral devices (or to proliferative memory or other similar device interface connected to the shared bus computer) the clock signal from the response of system registers for peripheral devices can twist with DO issuing response exchange unit 3 through the timing unit 6 to about boiling computer bus. This situation is determined by the second decoder 12, which analyzes the state of the common computer bus and the peripheral system trunk. In this case, the deshirator 12 at its output generates a start signal of the node 10 for capturing the main line only in the case when the signal from block 6 is present at its second input and there is no signal at the first input connected to the output of block 3 The element 16 that is fed to one of the inputs from the element ШШ 14, the signal from the output of the decoder 12 passes to the input of the installation of the flip-flop 18, and sets the latter to a single state. At the same time, this signal, via the HJDi 15 element, starts the node 10 of the line capture, which performs the operations of capturing the common EPM bus and interrupting the current program. At the same time, at the permitting output, node 10 generates a signal, including switches - switch 13 for transmitting to the computer via common bus data lines through block 6 of the query word formed by register 5 and modified by flip-flop 18. After receiving the query word in the computer, the node 10 resets the control signal of the switch 13 and returns to the initial state. Since the control signal of the switch 13 also arrives at the reset input of the trigger 18. failure, then resetting this signal returns to the initial state and the trigger 18. As a result, the computer proceeds to the interrupt service program from this mate on failure or malfunction. In this case, if the device for interfacing sends a response clock signal to the common bus of the computer before other devices on the common bus, the failure is detected by another similar device, having a similar control circuit, to which the computer simultaneously turned. Claim 1. A device for interfacing a peripheral device with a computer, comprising an exchange control unit, a control register, a first decoder, a first switch, a number register, two gain blocks, the group of information inputs-outputs of the first gain block forming the input-output groups of the device for connections to a group of information, address and command inputs / outputs of a computer; a group of information inputs / outputs of a second gain block forms a group of inputs / outputs of a device for connecting to an information group the peripheral device, the first group of information outputs of the third gain block and the group of outputs of the control register are connected to the first group of information inputs of the first gain block, the first group of information outputs of which are connected to the first group of information inputs of the control register and with the first group of information inputs of the second gain block, the second rjaynna. the information outputs of which are connected to the second group of information inputs of the control register, the sync of the synchronous inputs and the first output of which are connected respectively with. the first group of outputs and the first 5N input of the logical condition of the control unit of the obmek, the second group of outputs and the first group of inputs of the logical condition of which are connected respectively to the second group of information inputs and the third group of information: outputs of the second power block 3, the third of the group of information inputs of which are connected With the first group of information inputs, the first decoder and with the group of information outputs of the first switch, the group of information inputs of the first switch is connected to the second group The information outputs of the first gain block, a group of outputs of the register, are connected to the second group of information inputs of the first decoder, characterized in that, to increase reliability by providing hardware operational control of the operation, an address selector, a second switch, an address register, a capture node are entered into the device. a highway, a second decoder, a trigger c6oHj, two elements AND, two elements OR, while the third group of outputs of the exchange control block is connected to the third section; The T1PI information inputs of the second decoder and the second group of information inputs of the first gain unit, a third group of information outputs of which are connected to the second group of inputs of the logical condition of the exchange control unit Ms the second, third, fourth inputs of the logical condition of which are connected respectively to the first, second, third the outputs of the first decoder and the first, second, third inputs of the first element IL, the output of which is connected to the first input of the first element I, the second input of which is connected to the output of second decoder, the second group of information inputs of which are connected to the fourth group of information codes of the first gain unit, whose information output and information input of which are connected respectively to the capture confirmation input to the output of the capture node of the trunk gripper, allowing the output of which is connected to the zero input the trigger trigger and with the control input of the second switch, the group of information inputs and the other output are connected respectively to the group of outputs of the number register and the first g The information inputs of the first gain unit, the control input of the first switch are connected to the output of the address selector, the first and second groups of information inputs of which are connected respectively to the output register group of the address register and to the second group of information outputs of the first gain block; the output of the second element OR, the first input of which is connected to the output of the second element AND, the first input of which is connected to the information output of the second gain unit, nformatsionny second switch input coupled to the output latch SRB, a single input connected to the output of the first AND gate and with vtorm input of the second OR gate, the second output control register connected to a second input of the second element I. 2. The device according to claim 1, characterized in that the exchange control unit contains a trigger, five AND elements, two OR elements, a NOT element, two delay elements, the first input of the first OR element, the second input of the first RSHI element connected to the first the input of the first element And, and the zero input of the trigger form the first group of inputs of the logical condition of the block, the first one; The second element And the second input of the second element And connected to the first inputs of the third and fourth elements And form the second group of inputs of the logical condition of the block, the third input of the first element OR is the first input of the logical condition of the block, the third input of the second element And is connected to the first input the second element ShBi and is the second input of the logic condition of the block, the second input of the third element And is connected to the second input of the second element OR, and is the third input of the logical condition of the block, the second input of the fourth element And is connected to the third input. the house of the second element I.1Sh and is the fourth input of the logical condition of the block, the output of the first delay element, the first inputs of the first element OR and the second element AND form the first group of outputs of the block, the output The first element And the trigger output and the first input of the second element form the second group of outputs of the block, the outputs of the second delay element and the fifth element of And form the third: group of outputs of the block, while in the exchange control block the second input of the first element And is connected to the output of the element NOT whose input is connected to the trigger sync and with the output of the second element AND, the output of the first element OR is connected to the first input of the fifth element AND, the second input of which is connected to the output of the second element OR, the outputs of the third and fourth elements AND are connected respectively to the inputs of the first and second delay elements, the information input of the trigger is connected to bus unit capacity of the device. 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