SU1571599A1 - Device for interfacing processor and multiunit memory - Google Patents

Abstract

The invention relates to computing and can be used to organize multi-input multi-block memory when building multiprocessor computing systems based on mini and microcomputers. The purpose of the invention is to expand the functionality by allowing one word of data to be written simultaneously in N memory blocks and performing, when reading a logical OR operation, on data at any address in each of N memory blocks, improving speed by asynchronous exchange with memory and improving the reliability of the system by generating an error signal when accessing a non-existent memory cell. A device containing an array number register, an address decoder, a segment decoder, a data bus switch and a low-order address bus, the first AND element, a priority capture trigger, a system lock bus, channel transceivers for communication with the processor and the memory block, entered the number register segment, specifying the location of the segment in the address space of the processor, channel transceivers for communication with the processor of the register of the segment number, the OR element and the second AND element, which, together with the first AND element, trigger m priority acquisition and system bus locks resolve conflicts that arise when simultaneously accessing the memory of two or more processors connected through the device to a block of common first and second memory, AND-NOT elements and a delay element, allowing to increase the reliability of the system by issuing error signaling when accessing a non-existent memory cell. Several common memory blocks can be connected to each of the system processors. In order to multiply the information in K memory blocks or perform a logical operation in read mode OR the segment number registers of the interfacing devices connected to these K memory blocks are tuned to the same segment number, and the array numbers may be different. 2 Il.

Description

The invention relates to computing and can be used for organizing multiple-input multi-block memory when building multiprocessor computing systems based on mini- and microcomputers.

The purpose of the invention is to expand the functionality by providing an opportunity to record one

data words simultaneously in N memory blocks and execution when reading a logical OR operation on data at any address in each of N memory blocks, improving speed by asynchronous exchange with memory and improving system reliability by generating an error signal when accessing a non-existent cell - memory block.

Figure 1 presents the block diagram of the proposed device; Fig. 2 is a block diagram of a device of a multi-input multi-block system memory. we.

Device 1 contains a segment decoder 2, an address decoder 3, an array number register 4, a segment number register 5, a data bus and low-order data bus switch 6, a priority capture trigger 7, AND 8 element, OR element Y, AND 10 element, element AND-NOT 11, element-NOT 12. Element 13 of the delay node 14 channel receivers, nodes 15-18 channel receivers and transmitters of communication with the processor, processor channel 19, memory block 20, Record signal (RF) line 21 5 signal line 22 Read (THU) and signal line 23 Address synchronization (CIA), a group of control inputs 24 and the corresponding lines 25-27 of the output signal group of the access to the memory block 20, the signal line 28. exchange confirmation (CIP) with memory block 20, system bus line lock (SSB) 29, and, in, register register 4 of the array number is connected to the output of node 17 of channel receivers, and outputs to the higher bits of bus 30 of address block 20 of memory these and with the information inputs of the node 18 channel transmitters, the inputs of the register 5 segment number are connected to the outputs of the node 15 channel receivers

 and outputs - with informational inputs of the node of 16 channel transmitters and with inputs of 31 decoder 2 segments,

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five

Q

0

five

0

five

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five

inputs 32 of which are connected to the higher bits of the processor address bus 33 and information inputs 34 of the address decoder 3, inputs 35 of which are connected to the lower bits of the processor address bus 36 and inputs 37 of the switch 6, outputs 38 of which are connected to the younger bits of the block address bus 39 20 memories, information inputs of nodes 15 and 17 channel receivers and outputs of nodes 16 and 18 channel transmitters are connected to a bi-directional bus 40 of processor data and to the first inputs-outputs of switch 6, the second inputs-outputs of which are connected to bidirectional data bus 41 of memory block 20, lines 21-23 are connected to the control inputs of the address decoder 3, the outputs 42-45 of which are connected respectively to the enabling inputs of nodes 15-18 of channel receivers and transmitters, CIA line 23 is connected to input 46 element 10, the output of which is connected to the control input 47 of the decoder segment 2, the output 48 of which is connected to the input 49 of the element 2I 8, the inverse input 50 of the element OR 9 and the inverse input 51 of setting the priority capture trigger to 7, the output of the element 8 is connected with information 52 and strobe 53 inputs of the priority capture trigger 7, the inverse output 54 of which is connected to the RMS line 29, the AND element input 55 and the OR element input 56, the output of which 9 is connected to the processor standby input 57, the direct output 58 of the trigger 7 priority is connected to input 59 of the element OR-.9 and informational 60 and permitting 61 inputs of the switch 6, information output 62 of which is connected to the enabling input of the node 14 channel transceivers, in addition, output 58 of the trigger 7 of the priority capture is connected to input 63 of the I- element lffi 11, entrance 6 4 elements AND-NO 12 and input element 13, Support, the output of which is connected to the input 65 of the element AND-NO 12, the output of the element AND-NO 11 is connected to the input 66 of the element 10 And the input 67 of the element AND-NOT 12, the output of which is connected with line 68 of the error signal of the processor.

The device works as follows.

51

The address space of the processor is partitioned. Each segment is assigned a memory block of the required block. In each case, the segments can

have a variable size. The memory unit 20 consists of standard single-input memory modules, the outputs of which are parallelized and form the outputs 69 of the memory unit 20. The volume of each memory block 20 is divided into equal parts by volume - memory banks 70, and the bank volume 70.pami is equal to the size of the memory segment. The location of the segment in the address space of the processor is determined by the contents of register 5 of the segment number. It occupies a part of the address space through which the processor has access to the equal in volume array of the memory block 20, whose number is determined by the value of register 4 of the array number. The processor is connected to the memory blocks 20 through special interface devices 1, the function of which is to analyze the capture of the memory block 20 by another processor, if not, the capture of the free memory block 20 and output to the system bus of the lockout signal a priority for others processors connected to this memory block 20, outputting to the processor, accessing the captured memory block 20, a signal waiting for the processor via line 57, issuing an error signal via line 68 when the processor accesses a non-existent memory cell, switch and the channel processor 19 with memory unit 20 at the time of referring to the processor unit and the common memory address conversion, supplied from the CPU. Thus, device 1 replaces the higher bits of the memory supplied by the processor with the contents of register 4 of the array number, the value of which is set — by the processor by software. At certain points in time, the contents of registers 4 and 5 in each device 1 can be different, and the processor gets access to any array of memory blocks 20, but one array from each block 20, and the numbers of the arrays and the location of the corresponding segments can be arbitrary and changed programmatically during the repro process

sheni task. To connect the processors to one single-input memory block I / O devices 69

, 1 mates are paralleled and connected to the inputs-codes of the memory block 20, with the lines 29 of the mating devices 1 being connected, forming the system bus interlock. Appeal

0 processors to a shared memory block can only be performed sequentially, when one of the processors acquires a shared memory, the other processors do not have access to it. If the memory is free, and this is indicated by the presence of 1 on line 29 of the SNB, the processor, accessing the shared memory, captures the highest priority, and the interfacing device 1 sets the level O on the line of SNB, thus the other processors be captured. If now any processor accesses the captured memory, then

25

The device 1 corresponding to this processor generates an idle signal of this processor on line 57 with the level O, thus making it necessary either to repeat the call

to the memory, or to expect the release of the given memory block 20, lengthening the channel cycle of the memory access. It all depends on the capabilities of the processor — if the processor cannot lengthen the memory access cycle, a second memory access is necessary.

By dividing the entire memory into independent blocks, many

A go-go multi-block divided memory. However, in addition to the shared memory, the processor may have a memory with the usual organization, but in this case, the register 5 of the segment number

must be configured so that addresses that are not used by conventional memory are used. Since the processor has N segments, and therefore N memory blocks, where each of the memory blocks is common to several processors, the probability that two or more processors turn to one memory block, depending on the number

memory blocks and at large N is a small value, P

Ј 1 / mch. This greatly increases the efficiency of using the total

memory and reduces processor downtime due to the processor waiting for the memory block captured by another processor to be released.

In order to multiply the information in K blocks 20 of memory, registers 5 of segment 1 of device 1; connected to these K blocks of memory, are tuned to the same segment number, and the numbers of the arrays can be different. Now, when writing data to any address inside the number of the information segment set in registers 5, it will be recorded in all K memory blocks 20 at the addresses determined by the contents of the registers 4 numbers of the array. If, however, at least one of the K memory blocks 20 is occupied, then the devices 1 corresponding to these memory blocks generate an idle signal via line 57, and the processor waits for the memory of the occupied memory blocks 20, lengthening the channel memory access cycle. As the memory blocks 20 are freed, device 1 captures the freed memory blocks, sets the zero level on the system bus line 29, and removes the wait signal from line 57. However, the processor will wait for the end of the exchange with all the K memory blocks 20, since the outputs of the elements OR 9 of all devices 1 are made according to the open-collector circuit and are connected to one bus 57 of the processor wait. Implemented mounting OR 57 lines of waiting for all 1 interface devices connected to this processor. After the data is written to the free or empty memory blocks 20, device 1, by means of an acknowledgment signal, exchanges the CIP with the memory block, releases this memory block by setting a single level on the SBV, freeing the memory blocks without waiting for the end of the exchange with other memory blocks or terminating maintenance of occupied memory blocks. Thus, an asynchronous exchange mode is implemented, it also allows the use of memory blocks with different speeds. To perform a logical operation OR on the given 5 memory in K memory blocks 20, the segment number registers 5 also need to be set to one and same

five

segment number. The OR operation is carried out by implementing the mounting OR bus 40 of the data of device 1, since the inputs / outputs 71 of all devices 1 connected to channel 19 of the processor are paralleled.

The increase in speed during reproduction of information in K blocks of memory 20 or when performing an OR operation over data stored in K memory blocks will be K times if all K blocks were free (KQ) times if there was an access to memory blocks, where Q is the maximum number of processors already waiting for the release of one of the memory blocks required by the first processor. The probability that Q 1 is small and is determined by

P ratio

but

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The use of a device for parallel recording of information in K memory blocks allows organizing a hot backup mode of information stored in the system memory. In case of failure or loss of information in one of the memory blocks, information can be restored from the backup unit or the failed unit can be disabled. The availability of backup copies of the information allows for the majorization mode. This greatly increases the reliability of the entire system and does not lead to a system crash. In addition, in order to increase the reliability of the system, an error signal generation scheme is used when the processor accesses a non-existent cell of the memory block 20. The error signal generation circuit consists of elements 11-13. If, after the acquisition of memory block 20 and the generation of an RAP or CT signal, the memory block does not generate an SIR signal during the time period determined by delay element 13, which may mean that the processor accesses a non-existent memory unit cell, then at the output of the NAND 12 element, a zero-level error signal is output to the processor channel 19 via line 68. The outputs of the NANDM elements of all devices 1 are also made according to the open collector circuit and connected to signal lines 68 processor errors.

At the moment of switching on the device 1, registers 4 numbers of the maggive and registers

5, the segment numbers are set to the zero state, and processors through the zero memory segment have access to the zero memory blocks 20. Before exchanging processors with multi-input multi-block memory, it is necessary to set 4 array numbers in registers 4 on array numbers to the required arrays of blocks 20, and on segment 5 registers to segment numbers the memory segment numbers. For this, the processor sets the register address to 4 numbers array to the address bus. Address bus 33 and 36 enters the information inputs, respectively 34 and 35 of the decoder 3 addresses. After that, the processor issues a signal (SIL) to line 23, via which the decoder 3 decrypts the address set on address buses 33 and 36 and, after receiving control signals ZP or THU, respectively, from lines 21 and 22 produces a single signal to one of outputs 42- 45. If the decoder 3 receives the signal THU, then from output 45 a single signal arrives at the enabling input of node 18, allowing the information recorded on register 4 to pass through the processor data bus 40. In the ZP mode, the processor after the SIA signal sets the required value of the most significant bits of the array number to bus 40 and generates a ZP signal on which the decoder 3 outputs 44 a single signal to the enable input of node 17, and information from the processor data bus 40 is written to the register 4. Reading and writing to the registry number 5 of the segment number is carried out in the same way. After the mouth

The number of memory array numbers on registers of 4 segments on registers of 5 devices of 1 process can be addressed to any cell of installed arrays of memory blocks 20. At the same time, the processor does not feel the difference between the work of the multi-bypass memory and the memory with the usual organization, since the delay on device 1 is determined by the delay on the decoder 2, element 10, element 8, trigger 7, switch 6 and node 14, which is insignificant and does not violate the channel cycle of the processor accessing the memory.

The processor accesses the cell of the memory block 10 as follows.

0

The processor sends the address of the required memory cell to the address bus (33.36) and generates a CHA signal. The high-order bits of the address coming from the bus 33 addresses are fed to the input 32 of the decoder 2 segments of all 1 interfacing devices connected to this processor. The signal SIA from line 23 arrives at. input 46 elements AND 10 of all devices 1 of the same processor. A single level at the input 66 of the element And 10 bits prevents the passage of the signal SIA on the control

5 47 the input of the decoder 2 segments, since in the initial state the trigger 7 of the priority capture is reset and the SIP signal is in the zero state (respectively, inputs 63 and 28 of the element

0 AND NOT 11). With the arrival of the SIA signal, the 2 segment decoders compare the high-order bits of the address received from the bus 33 of the processor's addresses with the register bits of the 5 segment numbers, which are fed to the input 31 of the decoder 2.

If the high-order bits of the address match the contents of register 5 of the segment number, then the decoder 2 of this

® of device 1 generates a control single signal, which from output 48 goes to input 49 of element AND 8, inverse input 50 of element OR 9 and to inverted input 51 of the setting 0 |

5 trigger 7 capture priority. If line 29 of the system bus lock is set to O, i.e. this block of memory 20 has already been captured by another processor, then this O, enrolling

With input 55 of element 8, it blocks the installation of trigger 7 in one state, and also enters input 56 of element OR 12. For normal operation of device 1, it is necessary that 5 output 54 of trigger 7 of priority capture be open collector, i.e. in the presence of 1, this output did not affect the inputs connected to it, and in the presence of 0, this level was maintained at the inputs 55 and 56 of elements 8 and 9 and on the line 29 of the NSS. Since the trigger 7 has not yet been set to 1, the level O from the output 58 enters the input 59 of the element OR 9,

e the signal from the output of which with the level O enters the bus 57 waiting for the processor and informs the processor that for a normal continuation of an already started cycle, it is necessary to wait

11 15

termination of this signal. If level 1 is set on line 29 of SSB, i.e., memory block 20 is free at a given time, then level 1 from the output of the AND 8 element enters the information 52 and gate 53 inputs of the priority capture trigger 7, sets it to unity consisting. From the inverse output 54 of the trigger 7, the level O is fed to the input 56 of the element OR 9 and to the line 29 of the SB, together with other processors connected to this memory block, that this memory block is captured. The processor {capturing the memory block has the highest priority when working with this memory block | and no processor e can interrupt its operation with a finger. The processor's idle signal 57 on this device 1 does not expire, since the input 59 of the elec- tant 9 receives 1 from the direct output 58 of the trigger 7, maintaining the level 57 on line 57. T from the output 58 of the trigger 7 goes to information 60 and permitting 61 inputs of Switch 6, thereby commuting data bus 40 and lower bits of address bus 36, respectively, to buses 41 and 39 of the selected memory block-20. After the switch 6 triggers, the signal from output 62 goes to the enabling input of node 14, allowing control signals (RFP, THU, SIA) to pass through lines 21-23 to the same lines 25-27 and then to the control inputs of memory block 20. After that, the processor installs the necessary information on the data bus 40 and sends an RFK signal to line 21. At the same time, the information installed on data bus 40 and the lower bits of address bus 36 goes to buses 41 and 39. RFP signal goes through node 14 to line 25 and further to the control inputs of the memory unit 20. By the signal of the RFP, the information set on the data bus 41 is recorded in the cell of the memory block 20, whose address is set on buses 39 and 30. The information recorded in register 4 of the array number indicates the array number in memory block 20, and the address coming from processor for the lower bits of the address bus 39, indicates the address of the memory cell inside the array of block 20. Similarly, the processor reads information from memory block 20, but when

1599

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In this case, the processor issues a THU signal to the line 22 and through the node 14 to the line 26 and the control input of the memory unit 20.. Thereafter, the memory block 20 sets to the bus 41 the information that the processor reads from its data bus 40, producing a signal THU, to which the memory block 20 responds with a CIP signal.

The reproduction of information is carried out as follows. Possible There are 2 options.

Option 1. All K memory blocks 20 in which parallel recording is performed are not occupied. In registers 5, the segment numbers of all devices 1 connected to the required K memory blocks, the same is written

Q is the segment number. The processor then places an address on the buses 36 and 33 addresses within the set segment number and generates a BIA signal. Since all 20 memory blocks were

C are free, then the priority capture triggers 7 of all the required devices 1 are set to one. The 1m output 58 of the trigger 7 prohibits the input 59 of the element OR 9 from generating a processor idle signal on line 57 and enables the operation of the node of 14 channel receivers and the error signal generation circuit. The processor sets the data on the data bus 40 and generates an RFP signal,

5, line 21, which is fed to the inputs 25 of the required K memory blocks 20, and the data installed on the data bus 40, and the lower bits of the bus 36 addresses are received, respectively, on the 41 and 39 bars of the specified memory blocks 20. The higher address bits within the memory blocks may be different and are determined by the contents of the registers 4 of the array number. In response to the signal

5 GP, the memory block 20 generates an exchange acknowledgment signal with the CIP memory, which, from the output of the NAND 11 element, prohibits the generation of the error signal on the line 67 of the OR-PE 12 element

0 68 and using the element And 10 prohibits the operation of the decoder 2 segment. The output 48 of the decoder 2 switches- to the zero state and resets the priority capture trigger 7. System5 on the blocking bus goes into one state, allowing other processors to access this memory block, not waiting for the exchange operation to complete with the remaining (K-1) th

0

20 memory blocks. If the CIP signal N arrives during the interval defined by the delay of element 13, then at inputs 64, 65 and 67 of the element IS-NO 12 three 1 will be set, and element 12 will switch to the zero state, generating a processor access error signal on line 68 20 memories.

Option 2. At least one of the K memory blocks 20 is placed into which parallel recording is carried out. In this case, after the operation of the decoder 2 1 from the output 48, arriving at the inverse input 50 of the element OR 9, leads to the generation of a processor idle signal on line 57, since the trigger 7 and the SNB are in the zero state. As a result, the processor will wait for the release of this memory block, lengthening the channel cycle of handling the memory block. However, the free memory blocks 20 will complete the exchange with the processor, not waiting for the release of the occupied memory blocks 20. After the occupied memory block 20 is released, the wait signal is removed at the input 56, the trigger 7 is set and the memory block is captured. Further, the exchange process is carried out as described in option 1.

The logical operation of the SLI is performed in the same way as the information multiplication processor, only after issuing the address and the SIA signal, the processor generates the signal THB instead of the signal of the RFP and the data from the memory blocks 20 on the buses 41 through the switches 6 are sent to the processor data bus 40 where the mounting OR is performed over the read data. The OR operation is performed correctly only when all the K blocks of memory are free.

Claims (1)

Invention Formula Device for interfacing processor with multi-block memory containing array number register, address decoder, segment decoder, first node of channel transmitters, first and second nodes of channel receivers, data bus switch and lower address bus bits, first element And, priority capture trigger , moreover, the data input register of the array number is connected to the output of the first 0 five 0 five 0 0 five 0 five the node of the channel receivers, the output of the register of the array number is connected to the information input of the first node of the channel transmitters and connected to the output of the device for connecting the higher bits of the memory address bus, allowing the inputs of the first node of the channel receivers and the first node of the channel transmitters are connected respectively to the first and second outputs of the decoder addresses, and the information input of the first node of channel receivers and the output of the first node of channel transmitters are connected to the input-output of the device for connection to data processor and with the first information input / output of the data bus switch and the lower bits of the address bus, the second information input of which is connected to the first information input of the address decoder and connected to the input of the device to connect to the lower bits of the processor address bus, the first information output comm. The data bus and the lower bits of the address bus are connected to the output of the device for connecting to the lower bits of the memory address, the second information input-output of which is connected to the output of the device for connecting to the memory data bus, the second information input of the address decoder is connected to the first 5 information input of the segment decoder and connected to the input of the device for connecting processor addresses to the higher bits, the first, second and third synchronization inputs of the address decoder are connected to the device inputs Properties for switching to the synchronization buses, reading and writing the processor and connected to the corresponding inputs of the group of the second node of the channel receivers, the outputs of which are connected to the outputs of the device for connecting to the control inputs of the multi-block memory, the output of the segment decoder And with the R-input of the priority capture trigger, the output of the first element I is connected to the information and gate inputs of the priority capture trigger, the inverse output of which is connected to the output of the properties for connecting to the processor lockout bus and is connected to the second input of the first element AND, the forward output is trig The priority capture gera is connected to the enabling and third information inputs of the data bus switch and the lower address bits, the second output of which is connected to the enabling input of the second node of the channel receivers, characterized in that, in order to extend the functionality by providing the ability to record one word data simultaneously in N memory blocks and execution when reading a logical OR operation on data at any address in each of the N memory blocks, speeding up by asynchronous storage ena with memory and increase system reliability by generating an error signal when accessing a nonexistent cell | 5 memory, entered the register number of the segment, the third node of channel receivers, the second node of channel transmitters, the second element And, the first and second elements AND-NOT , OR element, delay element, the Output of the third node of the channel receiving — Iikov is connected to the information input of the register of the segment number, the output of which is connected to the second information input of the segment decoder: information input of the second node and channel transmitters, the output of which is connected to the outputs of the first channel transmitter and with information 0 five The third input of the channel receivers, allowing the inputs of the third channel receivers node and the second channel transmitters node, are connected respectively to the third and fourth outputs of the address decoder & the output of the segment decoder is connected to the inverse first input of the OR element, the second and third inputs of which are connected respectively to inverse and direct outputs of the priority capture trigger, the output of the OR element is connected to the output of the device for connection to the processor standby bus, the first input of the second element connected to the synchronization input of the address of the address decoder, and the output to the gate input of the segment decoder, the second input of the second element AND is connected to the first input of the first NAND element and the output of the second NAND element, the first input of which is connected to the input devices for connecting to the sync output of the memory unit, and the second input - with the direct output of the priority capture trigger, the second input of the first NAND element, and the input of the delay element, the output of which is connected to the third input of the first NAND element, whose output connected to the output of the device to connect to the input error signal processbra. five thirty FIG G FIG. I