SU1293861A1 - Device for monitoring duplicated system - Google Patents

Abstract

The invention can be used in automation and computing technology in building reliable computing systems. The purpose of the invention is to increase the speed of the control device and expand its field of application by controlling asynchronous computing processes. The device contains a transceiver unit and settings, a comparison node, a delay control node, and a first and second delay nodes. The transceiver unit and settings are connected to the backbone of the two computers and are configured by the machines either in the independent mode of the computer or in the duplicate mode. In the duplicate mode, the device receives data from one computer and puts it into standby mode, delaying the output of the Answer to trunk signal. At the same time, a delay control node is launched, generating a signal for the maximum allowable waiting time. If the second computer writes its data to the transceiver unit and the settings at a valid delay interval, the data is compared by the comparison node. If the data coincides, the delay control node removes the blocking of the delay nodes, allowing the Answer signal to be output to both trunks. In the event of a data mismatch or a data delay from one computer, a Response signal is output to the trunk of the data machine that entered the data and interrupt request signals are generated. Further error analysis is carried out by software. In the event of a single computer failing, the device correctly switches the device to the independent operation mode and continues its operation while the faulty computer recovers. 2 hp f-ly, 5 ill. C 9 (L o; o: o x

Description

one

The invention relates to computing and can be used to build reliable computing systems based on microprocessor sets.

The purpose of the invention is to increase the speed, in particular, the operation of controlling a duplicated computing system and expanding the field of application at the expense of asynchronous computing systems operating in asynchronous mode for exchanging over the backbone and clocked either from independent sources of clock pulses or without external clock generators.

FIG. 1 shows a functional diagram of the device, FIG. 2 is a functional diagram of the delay node in FIG. 3 — a functional diagram of the delay control node} in FIG. 4 is a functional diagram of a reception and transmission unit; FIG. 5 shows an example of implementation of a transceiver unit and settings on elements of the 588 series.

The device (Fig. 1) contains a transceiver unit 1 and settings, a comparison node 2, a delay control 3, a first 4 and a second 4 delay nodes. The device has the first and second inputs of EXCHANGE 5 and 5j, READ 6, and 6, RECORD / and 72, EXTERNAL DEVICE (WU) 8, and 8, ADDRESS 9, 1-9, ,, DATA 10, and 10 ,,, SELECTION CRYSTAL (VC) 11, and 11j, ELEMENTARY INSTALLATION 12 and 12 ,,, the first and second outputs RESPONSE 13 and rSj INTERRUPTION REQUEST (RR) and 14j, LOCK 15 and IS. Vlok. transceivers and settings has first and second information outputs 16 and 16j, response request request outputs 17, and 17, control outputs 18 and 18j, reset output 19, first and second response enable inputs 20 and 20, interrupt request input 21, diagnostic inputs 22, the control unit for delays has an input for receiving an error signal 23 and a blocking output 24.

The delay node (figure 2) contains the first 25 and second 26 elements OR, the elements NOT 27, the first 28 and the second 29 elements And, RS-trigger 30.

The delay control node (Fig. 3) contains an adder 31 modulo two, a third 32, and the first 33 elements OR,

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the third element And 34, the elements AND-NOT 35 and 36, the fourth element And 37, the second 38 delay element, the first to the fourth 39-42 D-triggers with dynamic control, the fifth element And 43 and the fourth element OR 44.

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The transceiver unit and the settings (figure 4) consists of two identical semi-sets, each of which contains the address selector 45, data register 46, state register 47, switch 48, sixth element And 49 with output 50, matching element (AH) 51 , the seventh element And 52, the output 50 of the element And 49 is connected to the Input of the readiness of the address selector, the output of the Readiness of the data register is connected to the outputs 15 (IS) and 17 (17) of the block, information output 16 (16j) is connected to the information output of the data register, and control output 18 (18) with the corresponding register output About, diagnostic inputs 23 are connected to the corresponding inputs of the switch, other groups of information inputs of which are connected to the information outputs of the data registers and the state of both semi sets, outputs Ready status register and the switch are connected to the corresponding inputs of the element 50, bus The data of each computer is connected to the information inputs of the data and status registers and the information outputs of the switch of its half-set, and the control inputs and outputs with the corresponding inputs of the selector the addresses, the control inputs 53-55 of which are connected to the control outputs of the 56 data and status registers, as well as the switch.

45 The specific type of connection of control inputs and outputs of the address selector, data register, status register and switch of each half-set is determined by the type of mag-

50 and the elemental base on which these elements are implemented. Element AND 52 is common to both half sets.

Figure 5 shows the implementation of the transceiver unit and settings on the LSI K588VGZ, K / KR588V1, K / KP588IR1, for simplicity, the formation-control circuit of parity bits and error signal processing are not shown

The transceiver unit and settings (figure 4) consists of two identical semi-sets, each of which contains an address selector 45, data register 46, state register 47, switch 48, sixth And 49 element with output 50, matching element (ESS) 51, the seventh element And 52, the output 50 of the element And 49 is connected to the Readiness input of the address selector, the Output Readiness of the data register is connected to the outputs 15 (IS) and 17 (17) of the block, information output 16 (16j) is connected to the information output of the data register, and output 18 (18) - with the corresponding register output No, diagnostic inputs 23 are connected to the corresponding inputs of the switch, other groups of information inputs of which are connected to the information outputs of the data registers and the state of both half sets, outputs Ready status register and the switch are connected to the corresponding inputs of the element 50, bus The data of each computer is connected to information the inputs of the data and status registers and the information outputs of the switch of its half-set, and the control inputs and outputs with the corresponding inputs of the selector a The addresses, the control inputs 53-55 of which are connected to the control outputs of the 56 data and status registers, as well as the switch.

The specific type of connection of the controllable inputs and outputs of the address selector, data register, status register and switch of each half-set is determined by the type of

straly and element base on which these elements are implemented. Element AND 52 is common to both half sets.

Figure 5 shows the implementation of the transceiver unit and settings on the LSI K588VGZ, K / KR588V1, K / KP588IR1, for simplicity, the formation - control of parity bits and error signal processing in the event of violation of information parity are not shown. Conclusions C2 to improve noise immunity can be connected to a potential of one. The data register is implemented on two multifunctional buffer registers К / КР588ИР1, but to simplify the device, output 17 is connected to only one output of the CI (recording is completed), the same way as the output pins of the main transceiver are used. Diagnostic signals at inputs 22 and status signals 18 are packaged into one eight-bit word for transmission to the processor.

This device is designed to control computers that carry out asynchronous exchange on their own lines in the Request-Response mode, and in addition, do not have a common source of clock signals. This allows protection from interference affecting the computer system, since the stages of operation of both computers are separated in time. The known devices of parallel programmable interfaces, direct memory access devices and various buffer nodes allow achieving similar results at the expense of significant computer time. The proposed device allows the operation to control and synchronize the computational processes in a single command to access the device.

The device is connected as an external device to the mains of both computers. Comparison of computational results is made not in every team, but only at control points chosen by the programmer, based on the requirements for the system's performance indicators and the reliability of its work. At each control operation, computer operation is synchronized with an accuracy of one command. If one computer fails and the computer fails to identify it, the computer is functioning properly, the system switches to independent operation mode, in which the device allows the computer to work without synchronization and comparison with the results of another computer. Such a translation excludes modification of the program when the system configuration changes. Setting the operation mode also allows switching to the highest mode 2938614.

communication with computer loading

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programs.

The device works as follows.

According to the initial setup signals, the memory elements of the transceiver unit 1 of the transceiver 1 and the settings and the node 3 of the control of delays are reset. The reset signal puts the device into the machine independent operation mode, which is determined by the zero signals at the outputs 18 of block 1.

To transfer the system to the duplication mode, both computers set a certain bit of registers 47 of block 1, then checking the state of the i47 registers determines that the device is in the duplicate mode. The peculiarity of block 1 is that only when writing to registers 46 in the duplicate mode, the machines are synchronized, the remaining blocks are accessed without synchronization.

When performing control operations, the necessary data is written to registers 46 of block 1. Writing data to each register 46 causes a zero signal to appear at the corresponding output 17 of block 1. If a zero signal arrives at a different output 17 at a valid time interval, then node 3 removes the signal interlocks at output 24. When the control data does not match, node 3 generates an interrupt request signal to both computers. In both cases, the machines continue their work. In the second case, they switch to the interrupt signal processing mode, for which, having determined the interrupt request code, they read information from the diagnostic outputs of node 3. The absence of an error when repeating the command causes the program to continue, otherwise a faulty computer is detected, which is transferred to the recovery mode , the control device is switched to the independent operation mode. After replacing or restoring the failed computer, a command for switching to duplicate mode is sent from the console. The working machine suspends its operations. The connected machine reads the necessary information from the memory of the working machine, further tuning is performed

control devices for duplication mode.

If it is impossible to determine within a predetermined time, which of the machines failed, in the presence of a stable mismatch of control data, an unrecoverable error signal is generated, and the machines carry out a safe stop program.

the left signal from one of the outputs 18. The use of two signals allows switching to the independent operation mode on a command of one machine, when the other, due to its failure, cannot perform such an operation.

The triggers of node 3 are unlocked only in duplicate mode. The first zero signal at one review is when the operation at the oral output of exit 17 causes a single

Control does not receive control data from one of the machines. After a certain interval after installing one of the signals at output 17, node 3 unlocks nodes 4., and 4 .., which allows the machine to continue operating, which set the signal at output 17. At the same time, an interrupt signal and a signal are set at one of the diagnostic outputs of the node 3, Analyzing the diagnostic information allows you to determine the cause of the interruption and go to the appropriate diagnostic program to identify the failed machine.

The delay unit (Fig. 2) operates as follows.

The initial setup signal sets the RS-flip-flop 30 to zero, and exits 18 to the zero state. As a result, the zero signal from output 11, generated when the corresponding data register of block 1 is set, regardless of the blocking signal 24, sets the RS-trigger 30 to one state, causing the formation of a response signal. When the zero signal is removed from the output 17, the RS flip-flop 30 returns to the zero state, removing the response signal. In the duplicated mode of operation, a single signal is supplied from the output 18 of unit 1. Now zero signal with

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a modulo two output signal of the adder 31, which arrives at the element OR 33, the delay time of which is determined by the allowable delay in the execution of control operations by computers. If the signal at the second output 17 of unit 1 is Wits before the signal at the output of the element OR 33, then the signal at D-BXO-de flip-flop 41 is set to zero, and the output 24 produces a zero signal to unblock the nodes 3. In case of an error, the comparison node generates a single signal at input 23, flip-flop 42 is set to state one and generates an interrupt signal at input 21 of block 1. Element 38 provides a trigger trigger delay before setting the signal at input 23. If the signal delay at the second output 17 of block 1 exceeds the allowed one, t The trigger 41, the blocking signal at the output 24 is removed and 35 one of the diagnostic triggers 39 and 40 is set, generating an interrupt request signal at the input 21 of the block 1.

The transceiver unit and the settings Q (figure 4) works as follows.

Consider the work of the first half. The address selector 45 reveals a call to one of the elements of the semi-stack, produces by

thirty

output 17 of unit 1 switches the RS-trig-45 control signals 55 connection

The state register 47 and the switch 48, regardless of the mode of the device when accessing them, expose the outputs Readiness zero signal, which through the element 49 goes to the Readiness input of the address selector 45, allowing the signal The answer to the highway. When writing control data to the data register, the latter sends a request for a response signal to the control node of hold 3 and establishes lockout 30 only if there is zero. signal at output 24. By removing the zero signal from output 17 of block 1, RS-flip-flop 30 returns to the initial state.

The delay control node operates as follows (FIG. 3).

 The initial setup signal sets all triggers to zero. Zero signals from outputs 18 of block 1 block the operation of all triggers through the elements AND 34 and AND-NOT 35. A zero signal from one of the outputs 18 is sufficient for the indicated blocking. The use of two signals allows switching to independent operation on the command of one machine when the other, due to its failure, cannot perform such an operation.

The triggers of node 3 are unlocked only in duplicate mode. First zero signal on od5

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a modulo-two output signal of the adder 31, which arrives at the element OR 33, the delay time of which is determined by the allowable delay in performing control operations by computers. If the signal at the second output 17 of unit 1 is Wits before the signal at the output of the element OR 33, then the signal at D-BXO-de flip-flop 41 is set to zero, and the output 24 produces a zero signal to unblock the nodes 3. In case of an error, the comparison node generates a single signal at input 23, trigger 42 is set to state one and generates an interrupt signal at input 21 of block 1. Element 38 provides a trigger trigger delay before setting the signal at input 23. If the signal delay at the second output 17 of block 1 exceeds the allowable one, triggered rigger 41 is removed the lock signal on the output 24 and one set of diagnostic 5 triggers 39 and 40 to form interrupt request signal input unit 21 1.

The transceiver unit and the settings Q (figure 4) works as follows.

Consider the work of the first half. The address selector 45 reveals a call to one of the elements of the semi-stack, produces by

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45 control signals 55 connection

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The state register 47 and the switch 48, regardless of the device’s operating mode, when they are accessed, are set at the outputs. Readiness. The zero signal that goes through the element 49 to the input Readiness of the address selector 45, permits signal response to the trunk. When writing control data to the data register, the latter sends a request for a response signal to the delay control node 3 and sets a lockout center.

signal at output 15 in order to block the driver of the permissible signal delay Response relative to the signal Exchange of its own computer. The response enable signal is fed to input 21 and then outputted by the address selector 45 to the trunk. Any information is read through the switch 48. The status register, besides storing the operating mode state, can be used to record various diagnostic information about the state of the machine, which allows other computers to use this information in error analysis mode.

Claims (3)

1. A device for controlling a duplicated system containing a comparison node, characterized in that, in order to improve speed and expand the field of application of the device, a transceiver unit and settings unit, a delay control node, a first second delay node, first and second inputs are entered into it , Read, Write, External Device Address Data, Fetch Chip, Initial Set Up, and First and Second Outputs Answer, Interrupt Request, Block Receive, Transmit, and Settings are connected to the corresponding lines. The first and second computers' main lines, respectively, the first and second information outputs of the transceiver unit and the settings are connected respectively to the first and second information inputs of the comparison node, the first control output and the first response request request output to the corresponding inputs of the control delay node and the first node delays, the second control output, and the second output of the response signal request — to the corresponding inputs of the delay control node and the second delay node; the reset output — to the corresponding moves delays of delay units and the control node, the first and second response enable signal inputs - the outputs of the first and second delay units, respectively, an interrupt request input and diagnostic outputs - to the respective outputs of the delay control unit, the input of which the error signal Priam pod8 0 five five 0 5 0 0 5 Q It is connected to the output of the comparison node, and the blocking output is connected to the blocking inputs of the delay nodes. 2. The device according to claim 1, that is, in that the delay node contains the first and second elements AND, two elements OR, the element NOT, the RS flip-flop, the input request signal of the node response signal is connected to the first inputs of the first and second elements OR, through the element NOT, to the first input of the first .I element, the second input of which is connected to the node reset input, and the output to the R input of the trigger, the blocking input of the node is connected to the second input of the first element OR, and the control input to the first input of the second OR element, the output of which is connected to the first input of the second element AND, the second input of which is connected to the output of the first OR element, and the output to the S input of the trigger, the inverse output of which is the output of the response enable signal node. 3. A device according to claim 1, characterized in that the control unit for delays contains a modulo two, third to fourth elements OR, third to fifth elements AND, first and second delay elements, elements OR NOT, AND-NO , the first through the fourth D-triggers with dynamic control, the first and second inputs of the request signal of the node response are connected respectively to the first and second inputs of the modulo two, the third OR element and the D inputs of the first and second triggers, the first and second controls input inputs - respectively to the first and The second inputs of the NAND element and the third AND element, the third input of which is connected through the first delay element to the output of the modulo two adder and the D input of the third trigger, and the output to the C input of this trigger, the input of the initial installation of the node to R- the inputs of the first, second and fourth flip-flops and to the first input of the fourth element AND, the second input of which is connected to the output of the third element OR, the first inputs of the fifth AND element and the OR-NOT element, the second input of which is connected to the output of the AND-NOT element and the output through the second delay element - to С -input the fourth trigger, the D-input of which is connected to the input receiving the error signal of the node, the R input of the third trigger is connected to the output of the fourth element I, the direct output to the C inputs of the first and second triggers, and the inverse output to the second input of the fifth AND element whose output is blocking / 7; f /. 20, 202 21 22 the output of the node, the direct outputs of the first, second and fourth flip-flops are connected to the corresponding diagnostic outputs of the node and to the inputs of the fifth OR element, the output of which is the output of the node interrupt request. 2d 2ft V /  - - 2 H FIG. one Lfl w At 20 -about ig, 2 0ut.3 "five Goth. J 56 55  g 51 e n 161 6 fbl / . .75, t g 4l8i  7 Wi S f First half set Second half / g fO 122.0 52 GW / h /BUT  // eight 22, 20 i Goth. 1- 43 50 1621 B21 0/5 fig L Compiled by V. Maksimov. Editor I. Segl. N. Tehred A. Kravchuk Proofreader A. Zimokosov 398/60 Circulation 802 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d. A / 5 Production and printing company, Uzhgorod, st. Project, 4 FIG. five