SU1365086A1 - Device for checking control units - Google Patents

Abstract

The invention relates to automation and computer technology and allows to expand the field of application of devices for controlling control units (CU) by providing the ability to control parallel CUs and increasing the monitoring capacity. The control unit for control unit contains registers 1 and 2, groups of elements AND 4.8 and 10, OR 7 and NOT 9, element EXCLUSIVE CAM OR 13, switching unit 14, control result triggers 6 and 11, group of triggers 3, elements OR 5 and 12. The device monitors the correspondence of signals, in parallel coming from the CU, to an allowable set of signals, a set of logical conditions and the required order. Each device cell, including a trigger group of triggers, AND, OR, NOT elements, upon receipt of a corresponding monitored signal, generates an acknowledgment signal or an error signal, depending on the state of the triggers subset and current values of logical conditions. The presence of such signals in the cells of the device is detected by triggers according to the control. 1 hp f-ly, 8 ill. five

Description

/ J

SAZ 05 01

ABOUT

oo

Oi

The invention relates to computing technology and is intended for use in systems for monitoring the correct functioning of control units of parallel computers.

The aim of the invention is to expand the scope of application by allowing control units of control to implement algorithms with different degrees of parallelism, and expanding the class of detectable defects.

FIG. 1 shows a diagram of the device; in fig. 2 - firmware microprogram; in fig. 3 shows an example of control of a parallel control algorithm according to a given operator circuit; in fig. 4 shows an embodiment of a switching unit; FIG. 5 shows an example 20 of the control unit control unit according to a predetermined information-logic scheme of the algorithm; in fig. 6 shows an example of pipeline control; in fig. 7 shows controllable switches; in fig. 8 is an example of setting up controlled switches.

The proposed device contains the first register 1, the second register 2, the trigger group 3.1-3.k, the first group of elements AND 4.1-4.k, the first element OR 5, the first trigger of the control result 6, the group of elements OR 7.1-7.k, the second a group of elements AND 8.1-8.k, a group of elements NOT 9.1-9.k, a third group of elements AND 10.1-10.k, a second trigger of the control result 11, a second element OR 12, an element EXCLUSIVE OR 13, a block 14 a group of elements OR 56.1 -56.1, the second group of elements OR 57.1-57.p, the last group of elements OR 58.1- pp. 58.p, the group of elements AND-NOT 59.1-59.1 input information th bus 60, output bus 61 and input bus 62 and the control 63 settings.

The managed switch of the second 10 group 16.1 (Fig. 76) contains the second group of elements AND 64.1-64.t, the first group of elements OR 65.1-65.p, the last group of elements OR 66.1-66.p, the first group of elements AND 67.1-15. 67.t, input information bus 68, output bus 69 and control input buses 70 and settings 71.

The purpose of the main device nodes is as follows

Register 1 is used to receive and store the characteristic values received from the monitored control block.

initiation of commands - controlled signals - vectors aa ... a1 ... a

V

25 where 1 (i- command initiated) or O, and the output of the i-ro register register 1 is connected to the first input of the element 4.1.1. The register 2 is designed to receive and store incoming values from the control object (for example, computer processors) condition values the process of the calculation is the vector P PI. . .R . . .P ,, where P 1 or 0. and also to control the switching unit 14 and the EXCLUSIVE element OR 13.

Triggers 3.1-3.k are used to display the process of receipt of monitored signals from the control unit

mutations containing the first group of pack-40 (control history storage),

equal switches 15.1-15.k, second group of controlled switches 16.1-16.k and setting register 17, input 18 monitored signals, input 19 logic conditions, first synchronization input 2045, second synchronization input 21, device reset input 22 , outputs of information about the result of control, error and confirmation of 23, 24 and 25 devices, respectively. gg

The circuit of the embodiment of the switching unit (Fig. 4) comprises a single potential bus 26, a control bus 27, first and second information input buses 28 and 29, output gg information buses 30-51, elements And 52-55.

The managed switch of the first group 15.1 (Fig. 7a) contains the first

the group of elements OR 56.1-56.1, the second group of elements OR 57.1-57.p, the last group of elements OR 58.1-58.p, the group of elements AND-NOT 59.1-59.1 the input information bus 60, the output bus 61 and the input control buses 62 and settings 63.

The managed switch of the second group 16.1 (Fig. 76) contains the second group of elements AND 64.1-64.t, the first group of elements OR 65.1-65.p, the last group of elements OR 66.1-66.p, the first group of elements AND 67.1- 67. t, input information bus 68, output bus 69 and control input buses 70 and settings 71.

The purpose of the main device nodes is as follows

Register 1 is used to receive and store the characteristic values received from the monitored control block.

initiation of commands - controlled signals - vectors aa ... a1 ... a

V

where 1 (i- command initiated) or O, and the output of the i-ro register register 1 is connected to the first input of the element 4.1.1. The register 2 is designed to receive and store incoming process conditions (for example, computer processors) from the control object calculations - vector P PI. . .R . . .P ,, where P 1 or 0. and also to control the switching unit 14 and the EXCLUSIVE element OR 13.

Triggers 3.1-3.k are used to display the process of receipt of monitored signals from the control unit.

having an internal memory of a device with a state vector C C ... C .... C where C is the trigger state 3.1.

Elements 4.1-4.k intended for testing the conditions for the possibility of initiating commands: generating signals confirming the correctness of initiating commands — vectors 3 a ... ... a ... a jHa output 23, where a 1 or O, respectively, when confirming and not confirming, and transferring the triggers 3.1-3.k to the new states.

Element OR 5, trigger 6, elements OR 12 and EXCLUSIVE OR 13 are used to generate an error signal at the output 24 if there is a defect in the right side of the calculation process.

The trigger 11 serves to form the output 25 of the signal of the presence of at least one confirmed command.

The elements OR 7.1-7.k and the elements AND 8.1-8.k are intended for transferring the triggers 3.1-3.k from state O to state 1 during the operation of the device.

The elements HE 9.1-9.k and the elements AND 10.1-lO.k serve to form the vector of error signals a d, ... dj. ... d when initiating the appropriate commands and failing to fulfill the conditions for the possibility of initiation, i.e. with a defect in the flow of control,

Switching unit 1A is intended for conditionally dependent (from vector P) switching of inverse outputs of flip-flops 3.1-3.k (elements of the set fCip and outputs of elements AND 4.1-4.k (elements of the set ajp respectively to the inputs of elements And 4.l-4.k and elements OR 7.1-7.k, ensuring the interaction of the device cells,

The device operates as follows.

Blocks 3.1, 4.1, 7.1, B.i, 9.1 and 10.1 form the first cell of the device, functioning according to FIG. 2, where Cj is the state of the trigger 3.1; state of 1st register register 1; a, is the output state of the element 4.1; d j is the output state of the AND 10.1 element; f; - conjunctions of signals on the group of inputs of the AND 4.1 element connected to block 14, called the function of the opportunity; f. - disjunctions of the signals at the inputs of the element OR 7.1, called the readiness function, with fl fi (iC; P, i and f. f;. (U, b P; |)) WHAT is set by the implementation and or setting of the switching unit 14.

Thus, the condition of the possibility of initiation and confirmation of correctness for the 1st team is:

al C.f, 1 7 a-. 1, C, O, (1) error signal generation condition:

a: (C; V f.) a; (C. f.) 1, d ,. 1, (2)

condition for transfer to 1 cell state:

C i f 1 C; 1 (3) and the analyzed value C is formed in the previous cycle.

After the device is put into operation, input 22 is given a reset signal to the original, translating the triggers 3.1-3.k-l, triggers 6 and 11, and registers 1 and 2 to zero, and trigger 3.k, which corresponds to the Start command, to one state.

The next launch of the device is carried out when the control unit generates the next group of commands and arrives at the input 18 of the device of their features, and the current vectors a and P. are written to registers 1 and 2 by the pulse at input 20 (i.e., in the first micro-cycle).

Those cells for which conditions (1) or (2) are fulfilled generate acknowledgment or error signals. Then, at the input 21, a synchronization pulse is formed (the second micro-tact), while those cells for which conditions (1) or (3) are fulfilled are transferred to new states, and triggers 6 and 11 form a signal, respectively, at outputs 24 and 25 errors:

D

(V d) V ((V a;) 0Pj

(four)

and confirmation signal: P

I v

(five)

the unit values of which, respectively, indicate the presence of a defect in the control unit and the presence of at least one confirmed command, P being the condition of the control unit being in the interrupt / stop state (PO 0) or operation (PC 1), the value of which is fed to the second input EXCLUSIVE OR 13.

The operation of the device is based on the principle of algorithmic control - tracking the flow of commands at the output of the controlled control unit to a given structure of the calculation algorithm. The algorithm is characterized by a set of participating commands and the order relations between them and is described by a scheme defined on the set of operators a; (converters, i.e., data processing commands, and discriminators, i.e., control transfer commands), among which the initial and final operators are distinguished. In operator schemes of algorithms (schemes with a given control, for example, shown in

FIG. As an operator, it is prescribed to execute after executing a certain set of predecessors and with the corresponding value of logical services. In the information-logic schemes of algorithms (calculation schemes or schemes without specified control, for example, shown in Fig. 56) it is indicated that a- can potentially be performed after the fulfillment of the corresponding predecessors (informational and logical) and conditions. In the general case, a command with a label. (Operator a;) can be initiated if all commands that are its predecessors in the informational, logical, and competitive sense are executed, and have corresponding commands. At the same time, for the multiple execution of commands, they are assigned different labels in accordance with the scheme of the algorithm, or, if possible, arrange a cycle with a count of repetitions.

To detect type 2 defects according to a given algorithm scheme for each

the circuit operator defines the functions fj and f; that indicate under what conditions the i-cell is set to 1 and after what conditions it can confirm the correctness of the command initiation and go to O.

The device implements testing of trigger functions for each command, and in contrast to the known use of trigger functions and asynonal

The corresponding values of the condition of the flowchart of the program diagrams are carried out by them and the process of calculations.

When the control flow of a command flow is generated, the following types of defects are possible:

1) the initiated command is not included in the set of commands used in this algorithm;

2) the initiated command violates the required order of commands following this calculation;

3) in the absence of an interrupt / shutdown, no command is generated (control hang);

4) when interrupting / stopping, the initiation of commands continues;

5) repeated false initiation of the command (sticking).

The device has the ability to detect defects of all listed types.

Type 1 defects are detected by setting f o (implementation or setting of switching unit 14 for cells corresponding to commands not participating in this algorithm. This ensures that they cannot be transferred to the ready state during the control of the algorithm.

Type 3 and 4 defects are detected in accordance with expressions (4) and (5) in blocks 5, 12, and 13.

Type 5 defects are detected due to the organization of the functioning of the cells, that after confirmation of the command, it is necessarily transferred over the control circuit of the algorithm from state G to state Om (a, - command labels), the table and can go to state 1 only in the second micro tact of the next clock cycle from the confirmation signals of others

settings (functions of the switching unit 14): illustrations of the settings (the vertex numbers of the graph correspond to the labels.

five

use for control purposes. In the device, testing of trigger functions is implemented (interpreted) by elements of 4.1–4.k, the state of the control variables is triggered by 3.1–3.k, the control variables are set to the appropriate state — by signals a depending on the previous states of the triggers, signals a and

0 specified by the switch communications between cells.

The duration of the first micro tact is chosen from the conditions of the end of transients in the logic circuits of the device and is equal to the delay in the memory register. The next start of the device with a pulse at the input 20 can take place almost immediately after the pulse at the input 21, i.e. overlap the second microtack. When using a device to control the pro-. control gram blocks whose command execution in computer processors

g takes a time much longer than the delay in the memory elements, we can assume that the control validation is carried out almost instantly, and the commands can be initiated at an arbitrary time, i.e. asynchronously, but with an interval not less than the device's takt time.

FIG. For, b, c, d are shown respectively

0

control circuit of the algorithm (a, - command labels), table

settings (functions of the switching unit 14): illustrations of the settings (the vertex numbers of the graph correspond to the labels.

thick solid lines show that to confirm the command corresponding to the cell in which the arc enters, it is necessary that C j 1 for the L-th cell from which the arc originates, thin solid (dashed) lines from the vertex i J, vertex j show that The j-cell is established unconditionally (conditionally) from signal a), and the operation table (t is the number of a clock; X is an arbitrary value of the logical condition; t 4, 5, b is another continuation of the process after step 3). The latter illustrates the operation of the device during the control of the control unit that implements this algorithm and form

followed by a failure, and the elements of the vectors are obtained in accordance with the program in FIG. 2. For example, the operator aJ can be executed after a and after a (with P, 1), the operator aj with after a (with Pj 1), and so on. the operator a can be executed if 8 is transferred to 1 by signal a (at P 0), transferred to O cells 5 and 10, set to 1 by signal a J, transferred to O that of cells 6 and 7, which was set

in 1 signal and with

corresponding P 2.

When configured according to a parallel scheme of the algorithm (as well as information-logic) at some point in time, condition (1) may not be fulfilled for all commands that have single functions of opportunity and unit states of cells. In other words, the control will be defect-free (in the sense of type 2 defects), if out of the multitude of commands that can be initiated (all the relevant conditions are fulfilled), only a few are generated by the control unit, for example, after confirming command a (FIG. 3) at any time, and the order of initiation of commands from the specified set can be arbitrary. Hence, it is believed that for a given setting, there are many functionally equivalent (giving the same result for the same data) control algorithms that differ (in the appropriate limits) by the degree of parallelism and order of operators, but controlled by the proposed device with the same efficiency.

(coverage of defect types) without reconfiguring it. For example, for FIG. 3 is the following (by command numbers, in brackets - parallel executables): k, 1 (2,3,4), (9,5,10), (2,6), 9,8 .. k, 1, 2,3,4,5,10,8,6,8 and others. For each of the algorithms of this set, initiating a false command according to condition (2) will result in an error signal at output 24. The proposed device configured to control a parallel algorithm scheme has advanced functionality.

An embodiment of switching unit 14 for monitoring according to FIG. 3 is shown in FIG. four.

The greatest effect from the use of the device is achieved when setting up according to the information logic algorithm (ILLA) scheme, which differs from the operator schemes in that it indicates only the informational and logical following relations between the operators. In this case, the switch configuration, i.e. obtaining the functions of capability and readiness, carried out by ILSA.

The standard scheme of the program in FIG. 3a corresponds to ILSA in FIG. 56, where thin solid arcs denote unconditional informational following relations, dashed ones - conditional informational following, thick - logical following relations. According to ILSA, operator a can be completed after a (entering the cycle) and after doing a and a in a loop, etc. The illustrations of the settings (similar to FIG. 3c) and the table of settings are shown in FIG. 5e, with the excessive links being excluded from the ILSA (for example, since a follows the ae, and a - a, the a - link is not taken into account). The device controls a number of equivalent algorithms that have a given ILSA (computing ILSA): k, 1,2,3,

(4,5) 6; k, (1,2), 3,4,5,3, (4,5), ..

.., 6; k, 2,1,3,5, 4,3 (4,5), 3,6, etc.

Since EMLA serves as the basis for parallelizing the algorithms and allows obtaining the most parallel algorithms, the device has the ability to control a class of equivalent algorithms from sequential to maximally parallel, which significantly expands the scope of application.

The device has enhanced functionality with the same efficiency and can be used to control control algorithms with an arbitrary degree of parallelism, including dynamic paralleling, when the one-D C is executed according to the combined drivers asynchronously in random order.

When monitoring conveyor control (for example, according to the program scheme in Fig. 6a), the device can have two settings depending on whether the asynchronous conveyor with variable conveyorism is controlled (by overlapping the following executions of the algorithm), as shown in FIG. 66 ,. c, d, or a synchronous conveyor with a constant conveyor; FIG. 6c, e, g. When checking the synchronous conveyor, the device stops confirming

correct initiation of commands of an independent switch.

probably from the controlled flow of control (stops the pipeline), if a defect like a failure has occurred in the command flow — not all commands in the group of synchronous commands (cycles 5, 6 and 6, 7) were initiated, i.e. possesses the increased controlling ability.

When configured according to the ILSA (parallel algorithm scheme), the device stores the information-logical structure of the calculation, and not the structure of the algo- rum; Control priority, but at the same time reveals type 1-5 defects for a whole class of control algorithms with varying degrees of parallelism duplication for each of these algorithms should be set to the corresponding backup machine.

The device allows control of the blocks controlling the calculations with a priori unknown (dynamic) parallelization of programs and algorithms, while self-verifiable duplication is not applicable.

The device allows you to control virtually any parallel control unit with a single setting method.

If the device performs control of multiprogrammed control units with a fixed set of programs, then, similarly to the method of combining operator algorithms, the algorithms are combined.

508610

(parallel, ILSA) by introducing into the set of additional logical conditions for the implementation of one or another algorithm, creating matrix schemes and eliminating redundant members, while taking into account syntactic and semantic coincidence of operators. Block 1A to the commutator. In particular, when combining two ILSA with non-intersecting sets of operators, all the connections between cells will depend on the value of the additional condition.

When monitoring multiprogrammed control units, the device detects system level defects — erroneous transitions to another

algorithm, since such defects are adequate to defects of type 1 and 2.

For the control of control units with a variable set of algorithms, the switching unit 14 is performed in the form of a pack switch 15.1 forms the function on the bus output 61 (c 1,2, ..., 1,1 ik)

;, a

c, v

(l ((p

, vr ,,; ,,) MP, vry)),

five

0

g

the state of the h th data input q is the number of conditions (bits

where C - women 60;

register 2); gg, o (AND g are the elements of the tuning vector R., which sets the code on the second inputs of the elements OR of the element group OR of the switch 15.1, the outputs of which are connected to the inputs of the AND-NOT element 59. n, and for the bit of register 2 one and only one pair of elements in the specified group of elements OR, such that the first inputs of the elements of the pair are connected respectively to the direct and inverse output of the oi-th register register 2, and the second inputs are received correspondingly

r, l ,,, and f. L f

1M

  ,one,

one

For the 1st cell

depending on the setting of R,

,,

g:

R.

, 2

R

; .., R; ,, where R ,.

  ABOUT

 H,

, 1.0

; ,, (, function f

,P

r; 1,0 (1, h, b1 f may not depend.

five

to depend unconditionally or conditionally (on a set of conditions) on the values of the chosen set C, j If C. enters f - unconditionally, then R j contains all 1. If C „does not enter f, then it is enough

for any pair of masks set G; . O (it is considered that P-i, 4 °° 0). If C is included in f, for a given condition value from 1 Pj (, then in vector R. masks are set to zero corresponding to the given condition values. Fig. 8 shows an example of setting up switches for controlling a given algorithm using the setup table in Fig. 5e ) when executing switches 15.1 and 16.1 complete, i.e. and n 2q. In the vector table, the settings for each vector R ,. indicate the components of its vector R;., not equal to O, and in brackets - the constituent elements of the vector R; equal to O. ZAHGi R Rj (r2) means that for the sixth cell f C (C P) set to 1 vector R, masking the group of OR elements connected by outputs to the NAND element, commuting C, in the R vector to specify all units except the mask r (index i, omitted), coming to the second input of the OR element, the first input which is connected to the output of the register bit 2, the corresponding (stored) value of P, the other vectors are zero .

The switch 16.1 forms a function on the SU output of the bus 69 (f 1,2, ..., m; m i k)

(v ((p, vu; ,,,) A (,))), "-

where a is the f-ro input state of bus 68; U; y, e (elements of the setting vector C.1, which sets the code on the second inputs of the elements OR of the element groups of the OR switch 16.1, whose outputs are connected to the inputs of the And element 67. "The switch 16.1 is configured in the same way as the switch 15.1 (FIG. 8), while

f:

W „

When the switching unit 14 is executed as a controlled switch during operation of the device, the vectors R and and are stored in register 17. When changing the set of programs executed by the control unit, the new values of the tuning vectors are entered into the register 17, setting the switching unit 14 and the device on the control of a new set of programs.

5 5 n

about g

five

0

The use of a full switch (1 mk, n 2q) is advisable when monitoring a set of strongly coupled algorithms, when the execution of each operator may depend on a variety of predecessors and conditions that, in practice, are usually specified by incomplete switching control (for example, 1), which significantly reduces redundancy.

It should be noted that the transition from circuit switching in the device to tuning from register 17 is similar to the transition from hard logic circuits to microprogram control. The proposed device differs favorably in processability because it has a regular structure (type cells and switches), which allows It can be implemented as an LSI homogeneous specialized processor. Managed switches can be made on W1M, and the device as a whole can be based on basic crystals. Another option is to perform non-switched elements on the matrices, and the switching unit 14 is implemented according to a predetermined set of controlled algorithms.

The most optimal application and. An embodiment of the invention is the use of a device for controlling parallel control blocks of specialized computers with a fixed set of calculation algorithms and a variable (dynamic) degree of parallelization of programs, the device being implemented in the form of an LSI programmable (customizable for production conditions).

The device has an increased monitoring ability, since it allows controlling the output signal flow of the control unit according to the condition of its correspondence to the free resources of the control object. For this, the conditions of free (busy) resources, for example, processors, which are part of the capabilities of the corresponding device cells, are entered into the set of (P) conditions for the flow of the computation process.

Let for ILSA in FIG. 55 the following distribution of resources by operators is specified: operators a, and a, - resource 1 (for example, an input / output device), a; and a resource 2, a and a, a resource 3. The condition of the free (busy) resources 1, 2 and 3 correspond to the single values (zero) of the conditions PJ, Pj and P, the Switch configuration tables, the functioning of the device and the switching configuration vectors are given respectively on fig.Zd and fig. 8, and. Cell 7 is used as a service cell (when operating C, 1) to obtain a conjunction that is not implemented directly by switches 15.1-15.1. For example, in step 2, FIG. 5, initialization is recognized

WG 0.

"Wrong because

etc.

When monitoring the control units and detecting defects in the command flow, the device generates an error signal at output 24, which can be used by the system to restart the program (for example, from a control point corresponding to the Start command in a controlled algorithm that is part of the entire program). The device is reset to. the initial one, and the register 17 records the tuning vectors corresponding to the next controlled control algorithm. The correct termination of the control algorithm can be determined by a confirmation signal, generated when operating as part of a system including a control unit, a control object, and a suggested cell that corresponds to the device, it is connected by input 18 to the output of the signs of initiation of control unit commands, input 19 to the output of the logical conditions of the object to the last operator of the algorithm (in particular, for the whole set of controlled algorithms, a special cell can be selected in the device, correlation (i.e. yn is input at 25 lo- vetstvuyuscha End command), and

control unit conditions), inputs 10, 21 and 22, respectively, to the outputs of the synchronization and system reset unit, outputs 24 and 25, respectively, to the input of the system interruption device and the input of the system mode indication device, and output 23 can be used either to fix the correct commands in the flow of control

neither, or (with full control according to the algorithm scheme) directly to control the control object, which in this case must include a register for receiving vector a, synchronized by pulses at input 21. The flow of vectors a at the output 23 of the device (Fig. 3.5-7 - operation table) is obtained as a result of decomposition of the flow of monitored signals into correct (confirmed) and erroneous. In other words, the proposed device corrects the input signal flow, followed by both. At the same time, the probability of issuing spurious signals at the output 23 is low, since the reliability of the device when executed as an LSI is significantly higher than the reliability of software control blocks, including RAM, decoders, registers, etc .; In addition, in order to emit false signals at the output 23, it is necessary that a failure (failure) should occur both in the control unit and in the proposed device

five

otherwise, the previous condition is not fulfilled.

When monitoring the control units and detecting defects in the command flow, the device generates an error signal at output 24, which can be used by the system to restart the program (for example, from a control point corresponding to the Start command in a controlled algorithm that is part of the entire program). The device is reset to. the initial one, and the register 17 records the tuning vectors corresponding to the next controlled control algorithm. The correct termination of the control algorithm can be determined by the confirmation signal generated by the cell corresponding to

matching cell

to the last operator of the algorithm (in particular, for the whole set of controlled algorithms a special cell can be selected in the device, with this signal it is set to 1 cell corresponding to the Start command.

Claims (1)

1. A device for controlling control units containing the first and second registers, a group of triggers, the first and second groups of elements AND, the first and second elements OR, the group of elements NOT, the first and second triggers of the control result, the information inputs of the first and second registers being connected respectively to the input of the monitored signals and the input of the logical conditions of the device, the synchronization inputs of the first and second registers are connected to the first synchronization input of the device, the output of the first element OR is connected to the D input of the The first control result trigger, the output of which is a device error output, the device reset input is connected to the R input of the first control result trigger, the R inputs from the first to (k -) th group triggers, and the S input of the k-ro group trigger where k is the input width of the monitored device signals, the device reset input is connected to the reset inputs first and second registers, exit The i-ro bit of the first register (, k) is connected to the first input of the i-ro element This first group, the second input of the i-ro element of the first group is connected to the single output of the 1st group trigger, the output of the i-ro element of the first group is connected to the R input of the i-ro group trigger, the second synchronization input of the device is connected to I first sync trigger inputs the result of the control and the first to the k-th group triggers, characterized in that, in order to expand the scope of application by providing the ability to control control blocks that implement algorithms with different degrees of parallelism and expand the class of detectable defects, the device contains a group of elements OR, the third group AND elements, the EXCLUSIVE OR element and the switching unit, the output of the second trigger of the monitoring result is the device confirmation output, the R input and the synchronization input of the second trigger are Control acetate are respectively connected to the reset input of the second I and the device synchronization input, the output of the second element OR is connected to the D input of the second trigger of the control result and the first input of the EXCLUSIVE OR element, the output of which is connected to the first input of the first OR element, the second input of the EXCLUSIVE OR element is connected to the output of the first digit of the second register, the direct and inverse outputs of the bits of the second register are connected to the group of control inputs of the switching unit, the group of inputs of the i-ro element I of the first group is connected to the i-th output bus of the first group of information output buses switching, inputs of the i-ro element OR group are connected to the i-th output bus of the second group of information output buses of the switching unit-, the output of the i-ro element OR group is connected to the first input of the i-ro element AND the second group, the output of the i-ro element And the second group is connected to the S input of the i-ro trigger of the group, the second input of the i-ro element And the second group is connected to the zero output of the i-ro trigger of the group, the output of the i-ro element And the first group through the i-th element of the NO group is connected to the first input of the i-ro element And the third group, the output of the 1st bit of the first register is connected to the second m input 1 i-ro element And the third group, the output of the i-ro element And the third group soy five 0 five 0 five 0 five 0 five dinen from () -m input of the first element OR, inverse outputs from the first to the k-th group trigger are connected to the first group of information inputs of the switching unit, outputs from the first to the k-th element And the first group are connected to the second group of information inputs of the switching unit, with a group of inputs of the second element OR, and form the output of information about the result of the control device. 2, The device according to claim 1, characterized in that the switching unit contains a setup register, the first and second groups of controlled switches, the group of control inputs of the switching unit connected to the input control buses of the controlled switches of the first and second groups, the outputs of the register bits the settings are connected to the input buses of the settings of the controlled switches of the first and second groups, the input information buses of the controlled switches of the first and second groups are connected respectively to the first and second groups of information x inputs of the switching unit, the i-ro output bus of the managed switch of the first group is connected to the i-th output bus of the first group of information output buses of the switching unit, the i-ro output bus of the controlled switch of the second group is connected to the i-th output bus of the second group of information output buses of the switching unit, the i-th managed switch of the first group contains the first group of 1 OR elements (1 k), from the second to the () -th group of n OR elements (n i2q, where q is the number of logical input bits device conditions) and a group of 1 elements in NAND whose outputs are connected to the first inputs of the corresponding OR elements of the first group, the second inputs of which form the input information bus of the i-ro controlled switch of the first group, the outputs of the OR elements of the first group form the output bus of the i-ro controlled switch of the first group, the inputs of the IS-NE group (1 1,1) are connected to the outputs of the OR elements of the () -th group, the first inputs of the OR elements from the second (1st) 1st groups form the input bus of the i-ro control switch of the first group , the second inputs of elements OR with in the second (1 + 1) -th groups form the input bus of the i-ro control switch of the first group, the i-th controlled switch of the second group contains the first and second groups of m elements And (wk), the group of n the OR elements, the outputs of the AND elements of the first group are connected to the first inputs of the corresponding AND elements of the second group, the second inputs of which form the input information bus of the i-ro controlled switch of the second group. di- l Ci Q  in the outputs of the elements And the second group form the output bus i-ro controlled switch of the second group, the inputs  of the element AND of the first group ((, ha) are connected to the outputs of the OR elements (groups, the first inputs of the elements SH from the first to ha groups form the input control bus of the i-ro controlled switch of the second group, the second inputs of the elements OR from the first to t) These groups form the i-ro configuration bus of the managed switch of the second group. di. Ci-0 in g (Pu2.3 2B gz but. di g FIG. five a, & 6odiy) i fli | Z: -y / y / i ZEESH J AL8Y & OD (1 a n c w w g I Xy: 7G #I 3rl fr but FIG. AT