JPS60140438A - System switching control system of information processing system - Google Patents

Abstract

PURPOSE:To quarantee easily the operation of system switching by providing a signal transmitting means for transmitting an interruption to the 2nd processing system in response to the error detection in the 1st processing system in the information processing system comprising the 1st and the 2nd processing systems. CONSTITUTION:An SVP interruption signal line 111, a forced stop signal line 113 and an interruption reception signal line 115 from the active system 1 and an SVP interruption signal line 112, a forced stop signal line 114 and an interruption reception signal line 116 from the standby system 51 are connected respectively to the other system. When the CPU or the SVP is faulty in the active system, an SVP interruption generating circuit 225 generates an output signal. Moreover, in case of all software errors, an SVP interruption signal is transmitted to the stand-by system via the line 111. On the other hand, in case of the stand-by system, when the SVP interruption is generated via the signal line 112, it is stored in a storage circuit 201, an interruption reception signal is transmitted to the active system and the interruption is informed to the software by an interruption generation circuit 205.

Description

[Detailed description of the invention] The present invention relates to a system switching control method for an information processing system.

As a means to improve the reliability of an information processing system, a configuration in which devices are duplicated, that is, a Duplex 7 stem is known. FIG. 1 shows a conceptual diagram of a Duplex system. This system is composed of an active system 1, a standby system 51, and an intersystem interface signal line 110 that connects the two systems. The active system 1 and the standby system 51 are systems that can each independently process information, but they do not need to have exactly the same configuration.

The active system 1 performs office operations, and the standby system 51 can be in several standby states. For example, there is a state where the power is not turned on. Now, some kind of failure occurs in the current system,
If it is determined that it is impossible to continue operations on the active system,
A highly reliable system that minimizes system downtime due to system failures by activating the standby system via the intersystem interface 110, transferring operations from the active system to the standby system, and continuing operations on the standby system. can be constructed.

A conventional system switching control method will be explained with reference to FIG. 2 showing an example of a duplex system. The active system 1 and the standby system 51 include a plurality of central processing units (CPUs) 2 and 53.
, main memory devices (MEM) 3 and 52, input/output control bags [(IOP) 4 and 55, and communication control device (IOA)
)5 and 56. Furthermore, this system has a switching device (SW) that is shared by these two systems.
) 102, a switching control device (SWC) 101, and various input/output devices 103-108. Various input/output devices include, for example, file-based magnetic disk devices and magnetic tape devices, as well as terminal-based card IJ-ders, line printers, bank teller terminals, and the like.

The SVPs of both systems are connected by an interface signal line 110. The interface signal line 110 is made up of a plurality of signal lines and includes an svp interrupt signal line and a reception signal line. Between 8VP6 and swc 101 (D signal fm40
The signal line 90 between the USVP 56 and the SWC 101 is a signal line for system switching instruction signals from each SVP. conduct. While the current system 1 is executing a task, the various input/output devices 103 to 108 connected to the 5W 102 are connected to the active system 1's l0P4 and IC via the signal lines 20 and 30 via the 8W 102.
Connected to A3.

System switching is performed when it is impossible for the active system 1 to continue business operations, and the reasons for this include, for example, an svp failure, a CPU failure, etc.
problems and software problems. Furthermore, I
When OPs and IOAs are also essential to the system, their failures can also be a factor in system switching. Current system 1 5VP6
5VP6 connects to the CP via the system bus 10 when
A failure report is made to U2, and CPU2 reports this to the software. The software in the active system 1 prepares for system switching and executes an instruction for the 5VP 6 to cause the 5VP 56 in the standby system 51 to generate an SVP interrupt. Also,
In the event of a software failure on the active system 1, the software prepares for system switchover, and the standby system 51
Executes an instruction that causes the VP56 to generate an svp interrupt. In addition, in the event of a failure of CPU2 in the active system, 5VP6
detects a failure and generates an SVP interrupt to the 5VP 56 of the standby system 51. On the other hand, the standby system 51 that accepted the sv'p interrupt
SVP of! 56 turns on the power if the standby system 51 is in a power-off state, loads the program if it is in a program load waiting state, starts the software, and connects the CPU 53.
, generates an interrupt. The CPU 53 reports the interrupt to the standby software, and the software executes a system switching command to the 5VP 56. 5VP56 is 5WC
A system switching instruction is issued to IOI, and 5WC101
Various input/output devices 103 to 10 connected to WI02
B is connected to the standby system 51. However, in this method, when switching systems in the event of an svp failure, the software executes an instruction that generates an SVP interrupt for the failed SVP, so its operation is not guaranteed. To guarantee this, SVP interrupt generation, intersystem interface control, and 1svp must be realized by independent hardware, which is a drawback.

Another method is when 5VP6 fails.

5VP6 reports the failure to CPU2 and the standby system 5
It is conceivable that an SVP interrupt be generated for one 8VP56. The CPU 2 reports the SvP failure to the software on the active system 1, and the active system 10 software prepares for system switching. On the other hand, the 5VP that accepted the SVP interrupt
56 starts the software of the standby system 51 and generates an interrupt to the CPO 53 in the same manner as described above. The CPU 53 reports the interrupt to the software of the standby system 51, and the software executes a system switching command to the 8VP 56. Thereafter, system switching is performed in the same manner as described above. In this method, s
When a vp failure occurs, the 8VP itself generates an SVP interrupt, so hardware independent of the SVP is not required to generate an SVP interrupt, but synchronization is performed between the active software and the standby software. There is a drawback that system switching may occur without the active software's knowledge or while the active software is executing a task, and file contents may be destroyed.

As a method for eliminating such drawbacks, the following method is available in which a simple interface is added between the two systems and synchronization is achieved between the two systems. In other words, a pair of forced stop signal lines are provided between the SVPs of both systems, and the software on the standby system 51 forces the active system 1 to stop instruction execution after receiving an SVP interrupt and before issuing a system switchover instruction. Issue a stop instruction command. The CPU 2 of the active system 1, which has been instructed to forcibly stop, immediately stops execution of subsequent instructions at the end of the currently executing instruction. As a result, the continuation of business operations after switching the active system 1 is eliminated. However, in such a system, the execution of the instruction is not unconditionally stopped when a forced stop instruction is issued, and the execution of the instruction is also stopped when a forced stop command is issued by mistake. It has the disadvantage of being stored away. For example, a software bug (insect) in the standby system 51 may cause a forced stop command to be issued to the active system 1 by mistake, or a hardware failure may cause the forced stop signal line to be activated. Sometimes, the normal active system 1 immediately stops.

An object of the present invention is to provide a system switching control method for an information processing system that eliminates the above-mentioned drawbacks.

The method of the present invention is a system switching control method for an information processing system having a first and a second processing system, in which the second (or second) processing system responds to failure detection in the first (or second) processing system. a first signal sending means provided in the first (or second) processing system to send an interrupt signal to the first processing system; a storage means provided in the (or second) processing system; and a forced stop signal for stopping the instruction execution operation of the first (or second) processing system in response to the interrupt signal. (or second
) a second signal sending means provided in the second (or first) processing system to send the signal to the first processing system based on the contents of the storage means and the forced stop signal. (
or the instruction execution operation of the second (second) processing system is stopped, and the second (or first) processing system
Continue processing of the processing system.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 3 shows intersystem interface signal lines in the present invention. From the active system 1, an SVP interrupt signal line 111, a forced stop signal line 113, and an interrupt reception signal line 115 are connected, and from the standby system 51, an SVP interrupt signal line 112 and a forced stop signal line 1 are connected.
14 and an interrupt acceptance signal line 116 are respectively connected to other systems.

FIG. 4 is a diagram showing a command to activate the forced stop signal line. The instruction length is 32 bits. Pit 〇-7 is an order (O
P) In the coat section #), here system call instruction 8
It is YC. Engineering 2 is auxiliary information for the command. It is 1 in hexadecimal.
By giving 5, it becomes a forced stop instruction command during a resystem e-call command. B1 indicates the value of the pace register during address modification, and α1 indicates 0 indicating the displacement software.
FIG. 5 is a diagram showing, on a time axis, the operations of the active system and standby system at the time of an SvP failure. Next, the operation of the system of the present invention in the event of an SvP failure will be explained with reference to FIGS. 2 and 5. When an SVP failure occurs in 8VP6 of active system 1, active system 1
It generates an internal machine check interrupt for the CPU 2, and also generates an SvP interrupt for the standby 5VP 56 via the inter-system interface 110'. CPU
2 generates an interrupt to the software, and the software performs processing that interrupts normal operations and stops the instruction.
Instructions may continue to be executed for some reason, such as a software bug. FIG. 5 shows such an example where instructions B, C, D and E are continued. On the other hand, the 5VP56 that accepted the svp interrupt
1'6, the interrupt reception is notified through the signal line 116, and an SVP interrupt is generated to the CPU 52, so that the CPU 52 interrupts the software. On the other hand, 8
In VP6, an interrupt request holding circuit is set to accept an interrupt via the signal line 116. The standby system software recognizes the 872 interrupt from the active system, prepares for system switching, and executes a forced stop command (syc command (I 2 = 15)) before actually issuing a system switch instruction, and stops the active system 1. In response to this stop instruction, if the interrupt request holding circuit is set, the 08 VP6 instructs the CPU 2 to stop the instruction.If the CPU 2 is currently executing an instruction for some reason, Instruction execution is stopped after the instruction being executed (in this example, instruction E) is completed. Therefore, from this point on, the CPU 2 (software) of the active system 1 does not perform any operations on the various input/output devices shared by the system. Do not perform.After this, the CPU 52 (software) of the standby system 51
executes a command to instruct swciol to switch systems, and various input/output devices 103 to 1 connected to 5W102
Connect 08 to the standby system.

Business can be resumed on the standby system. However, 8V
Even if a stop instruction is received when the interrupt request holding circuit is not set at P6, this stop instruction is ignored. In this way, even if a stop instruction is given by mistake, the system will still operate correctly.

FIG. 6 is a diagram showing an embodiment of the method of the present invention. In the figure, only the parts related to the present invention are shown, and other components (
For example, storage devices, arithmetic units, etc.) are omitted. In the figure, intersystem interface lines 111 to 116 are the SVP interrupt line to the standby system, the SVP interrupt signal line from the standby system, the forced stop signal line to the standby system, and the forced stop signal line from the standby system, respectively. The signal line is used to accept interrupts to the thread, and the signal line is used to accept interrupts from the standby system.

In this embodiment, a holding circuit 201. Mask circuit 202 that masks SVP interrupts (disables acceptance). A that generates an AND (logical product) condition for the outputs from the holding circuit 201 and the mask circuit 202
ND circuit 203. Other interrupt signal line group 207. An OR circuit 204 that generates an OR (logical sum) condition for various interrupt signal lines.
An interrupt generation circuit 2059 that is activated by the output of the OR circuit 204 and generates an interrupt to software; an interrupt holding circuit 2;
AND circuit 227.27 that generates an AND condition of the output signal from 227.27 and the signal from forced stop signal line 114. A holding circuit 211 that temporarily holds the output of the AND circuit 215. Other instruction stop signal lines $214゜OR circuit 212 that generates OR conditions for various instruction stop signal lines. An instruction stop control circuit 213 that is activated by the output of the OR circuit 212 and stops execution of the instruction at the end of the currently executing instruction. An instruction register 221 that stores one word of instructions to be executed by software; a decoder 222 that decodes the contents of the instruction register 221; a holding circuit 223 that temporarily holds the output signal when the decoder 222 decodes the svp interrupt generation instruction; SvP interrupt generation circuit 225 that generates an output when an 8VP failure or CPU failure occurs. An OR circuit 22 that generates an (OR) condition for the outputs of the holding circuit 223 and the SVP interrupt generation circuit 225.
6゜Interrupt holding circuit 227゜SVP interrupt signal 111 and the reception of interrupts from other systems are set by the signal 116゜Holding circuit that temporarily holds the output signal when the decoder 222 decodes the forced stop instruction command It is equipped with 224.

Although FIG. 6 shows the active system, it is assumed that the standby system has the same configuration.

In the active system, circuit 225 generates an outgoing signal if the CPU or SvP fails. Also.

In case of software failure, the software
The interrupt generating instruction is executed, and the holding circuit 223 is set so that the decoder 222 decodes this instruction. In either case, send the SVP interrupt signal to line 111 to the standby system.
Send via.

On the other hand, considering FIG. 6 as a standby system, when an SvP interrupt occurs via the signal line 112, this interrupts the holding port path 201.
The mask bit of the mask circuit 202 is held at IQI.
Otherwise, an interrupt signal is generated from the AND circuit 203, a signal is sent to the active system to acknowledge the interrupt, and the interrupt generation circuit 205 notifies the shiftware of the interrupt.

The software investigates the cause of the interrupt, and when it recognizes the svp interrupt, executes a forced stop command (syc command (I 2 = 15)) to perform system switching and forcibly stop the active system. It decodes the command, temporarily holds the result in the holding circuit 224, and instructs the active system to forcibly stop via the signal line 113.

Again, consider Figure 6 as the current system. When the holding circuit 227 receives an interrupt reception signal via the signal line 116, it is reset by the interrupt signal that has already been output to the signal line 111, and holds that the active system has issued an interrupt request. . In this state, when a forced stop is instructed by a forced stop signal given from the standby system via the signal line 114, the timekeeping circuit 227
is set, this forced stop signal is temporarily held in the holding circuit 211 via the AND circuit 215,
It is applied to the command stop control circuit 213 via the zero-pass circuit 212. This circuit 213 interrupts and stops execution of the next and subsequent instructions at the end of the currently executing instruction. on the other hand,
Due to some reason such as a bug in the standby software,
Even if a forced stop is erroneously instructed to the active system via the signal line 114, the holding circuit 227 of the active system is not in the set state, so the forced stop signal does not pass through the AND circuit 215 and is sent to the instruction stop control circuit. doesn't work.

The present invention has the effect of easily guaranteeing system switching operation with the addition of a small amount of hardware.

[Brief explanation of the drawing]

Fig. 1 is a conceptual diagram of a duplex system, Fig. 2 is a block diagram showing an example of a duplex/stem, Fig. 3 is a block diagram showing intersystem interface signal lines of a duplex system according to the method of the present invention, and Fig. 4 is a block diagram showing an example of a duplex/stem. FIG. 5 is a time chart showing the operation according to the method of the present invention, and FIG. 6 is a block diagram showing an embodiment for carrying out the method of the present invention. In the diagram, 1...current system, 2553-・group・
Central processing unit, 3, 52...Main storage device, 4.
55... Input/output control device, 5.54...
・Communication control device, 6.56...Monitoring device #, 10
．． 60...System bus, 20, 30, 40
,70,80,90,120°130.140,150
, 160, 170...--Signal line. 110-116...Inter-system interface signal line, 101...Switching control device, 102...
・Switching device. 103-108... Input/output equipment, 201, 21
1゜223.224,227...Holding circuit, 2
02...Mask circuit, 203, 215...
・・AND circuit, 204°212.226・・・・・・
OR circuit, 205... Interrupt generation circuit, 213.
...Instruction stop control circuit, 221 ...Register, 222 ...Decoder. Me l Figure Z Figure 3 Figure 4

Claims (1)

[Claims] In a system switching control method for an information processing system having a first and a second processing system, the second (or first) processing system responds to failure detection in the first (or second) processing system. a first signal sending means provided in the first (or second) processing system to send an interrupt signal to the processing system; and a first signal sending means provided in the first (or second) processing system to send an interrupt signal to A storage means provided in the processing system and a forced stop signal for stopping the instruction execution operation of the first (or second) processing system in response to the interrupt signal are sent to the first (or second) processing system. a second signal sending means provided in the second (or first) processing system to send the signal to the processing system; The instruction execution operation of the second (or first) processing system is stopped.
System switching control method O for an information processing system, characterized in that the processing system of ) continues the processing of the first (or second) processing system.