JPS6079438A - System switching control system of information processing system - Google Patents

Abstract

PURPOSE:To perform system switching operation in safety by allowing one processing system to send out an interruption signal to an other processing system on detecting its trouble, and allowing the other processing system to send out a stop signal for instruction executing operation to the former system and then carry on the processing. CONSTITUTION:An in-use system 1 and a stand-by system 51 consists of CPUs 2 and 53, monitoring devices 6 and 56, etc., and share a switching device 102, input/output equipment 103-108, etc. If a fault occurs in the device 6 firstly, an interruption for the internal machine check on the CPU2 is initiated and an interruption to the device 56 is caused; and the CPU2 stops after executing an instruction instantaneously or only a prescribed instruction, and the CPU52 on receiving the interruption of the device 56 executes a forcible indication instruction and then switches systems through the device 102 to connect equipments 103-108 to the stand-by system, thereby restarting the business. Consequently, the safety of the switching operation between the systems is securely by adding small hardware.

Description

[Detailed description of the invention] The present invention relates to a system switching control method for an information processing system.

2. Description of the Related Art As a means for improving the reliability of an information processing system, a duplex system, which has a configuration in which devices are duplicated, is known.

Figure 1 shows a conceptual diagram of a duplex system. This system uses an intersystem interface signal IIIi! that connects the active system 1 and the standby system 51 and both systems. 110. The active system 1 and the standby system 51 are systems that can each independently process information, but they do not need to have exactly the same configuration.

The active system 1 performs business operations, and the standby system 51 is in a standby state. Here, several states can be considered as the standby state. For example, the computer may be in a standby state without turning on the power, in a state in which the power is turned on and waiting to load a program, or in a state in which a program is loaded and a batch job is executed and on standby.

Now, if some kind of failure occurs in the active system and it is determined that it is impossible to continue the work on the active system, the standby system is activated via the intersystem interface signal line 110, and the system is switched from the active system to the standby system. By transferring all operations and continuing operations on a standby system, it is possible to build a highly reliable system that minimizes the number of system passes due to failures.

A conventional system switching control method will be explained with reference to FIG. 2 showing an example of a duplex system. The active system 1 and the standby system 51 include a plurality of central processing units (CPLI) 2 and 53, main memory devices (MEM) 3 and 52, input/output control devices (IOP) 4 and 55, and a communication control device (I
CA) 5 and 54, and monitoring devices (8VP) 6 and 56 that perform monitoring control and intersystem control of these devices.

Furthermore, this system includes a switching device ('8W) 102 and a switching control device (8WC) shared by these two systems.
101 and various input/output devices 103 to 108. Various input/output devices include, for example, file-based magnetic disk devices and magnetic tape molds, as well as terminal-based card readers, line printers, bank teller terminals, and the like. The SVPs of both systems are connected by an interface signal line 110. The interface signal line 110 is composed of a plurality of signal lines, and includes an SVP interrupt signal line and a reception signal line.

Signal lines 40 and 8 between 8VP6 and 5vvC101
Signal m90 between VP56 and 5WCIOI is a signal line for system switching instruction signal from each SVP, and 5W
CIOI connects each input/output device 103 to 1 via 5WI02
Switch the thread connected to 08.

During execution of work by the active system 1, each input/output device 103 to 108 connected to the 5W 102 connects to the l0P4 of the active system 1 via the signal lines 20 and 30 via the 5W 102.
and ICA3.

Thread switching is performed when it is impossible for the active system 1 to continue the work, but the reasons for this include, for example, SvP failure i, cPU
problems and software problems. Furthermore, I
When OP and ICA are also essential to the system, their failures can also become a factor in system switching. 8VP6 of active system 1
When a failure occurs, l'i, 5VP6 reports the failure to the CPU 2 via the system path 10, and the CPU 2 reports this to the software.

The software for the current yarn 1 prepares for system switching, and
An instruction is executed for the VP6 to cause an svp interrupt to be generated in the 8VP56 of the standby system 51. Also.

In the event of a software failure, the software prepares for system switching and executes an instruction for %5VP6 to cause the 5VP56 of the standby system 51 to generate an SVP interrupt. Also,
When a failure occurs in the CPU 2 of the active system 1, the SVP 6 detects the failure and generates an SvP interrupt to the 8VP 56 of the standby system 51. On the other hand, 8VP5 of the standby system 51 that accepted the SVP interrupt
6 turns on the power if the standby system 51 is in the power-off state, loads the program if it is in the program load waiting state, starts the software, and generates an interrupt to the CPU 53.

The interrupt is reported to the CPU53id standby system software, and the software executes a system switching command to the 8VP56. The 5VP 56 issues a system switching instruction to the 5WC 101, and the 5WCIOI connects the various input/output devices 103 to 108 connected to the 5W 102 to the standby system 51. However, in this method, when switching threads in the case of an SVP failure, the software executes an instruction that generates an 8VP interrupt for the SVP in failure, so its operation is not guaranteed. To guarantee this, the SVP interrupt generation and intersystem interface control must be realized by hardware independent of the SVP, which is a drawback.

In addition, as another method, when 5VP6 fails, 5VP6
reports the failure to CPU 2, and the standby system 51 5
It is possible to generate an SVP interrupt to the VP56. CPU2 performs SvP for the software of active system 1.
The failure is reported, and the software on the active system 1 prepares for system switching. On the other hand, SVP 56 that accepted the SVP interrupt
starts the software of the standby system 51 and generates an interrupt to the CPU 53 in the same manner as described above. CPU53 is standby system 5
The interrupt is reported to the software of SVP 56, and the software executes a system switching instruction to SVP 56. Thereafter, system switching is performed in the same manner as described above. In this method, SV
In the event of a P failure, the SVP itself generates an SVP interrupt, so hardware that is independent of SvP is not reliable in order to generate an SVP interrupt, but synchronization is performed between the active software and the standby thread software. Therefore, system switching may occur without the active software's knowledge or while the active software is executing a task, and there is a risk that the same files may be destroyed.

An object of the present invention is to provide a thread switching control method for an information processing system that eliminates the above-mentioned drawbacks.

The method of the present invention is a switching control method for an information processing system having a first and a second processing system.
) in response to a failure detected in the processing system, the first (or second) processing system sends an interrupt signal to the second (or first) processing system, and responds to the interrupt signal. a forced stop signal from the second (or first) processing system to the first (or second) processing system to stop the instruction execution operation of the first ('!taken second) processing system; After sending lc, the second (or first) processing system sends the first (or a↓2)
Continue processing of the processing system.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 3 shows intersystem interface signal lines in the present invention. An SVP interrupt signal line 111 and a forced stop signal line 113 are connected to the active thread 1, and an SVP interrupt signal line 112 and a forced stop signal line 114 are connected to the standby system 51, respectively, to other systems.

FIG. 4 is a diagram showing a command to activate the forced stop signal line. The instruction length is 32 bits. Bits 0-7 are instructions (O
P) code section, here system call instruction S
It is YC. -I2 is auxiliary information of the instruction, and by giving 15 in hexadecimal, it becomes a forced stop instruction instruction during a system call instruction. Bl indicates the value of the pace register at the time of address modification, and α1 indicates the displacement software.

FIG. 5 is a diagram showing the operations of the active system and standby system on a time axis when an SVP failure occurs.

Next, the operation of the system of the present invention in the event of an SVP failure will be explained with reference to FIGS. 2 and 5. Sv in 5VP6 of current system l
When a P fault occurs, an internal machine check interrupt is generated for the CPU 2 of the active system 1, and an SV is sent to the 5VP 56 of the standby system via the intersystem interface 110.
Generates a P interrupt. CPU2 generates an interrupt to software.

Although the software 7 performs processing to interrupt normal operations and stops the instructions, the instructions may continue to be executed due to some reason such as a software bug. In FIG. 5, such examples include instructions B and C.

The case where D and E are continued is shown. On the other hand, S
The 8VP56 that accepted the VP interrupt sends S to the CPU52.
A VP interrupt is generated, and the CPU 52 interrupts the software (-S
interrupt. The standby system software recognizes the SVP interrupt from the active system, prepares for system switching, and issues a forced stop command (SYC command (I2=1
5)) and instructs the CPU 2 of the active system 1 to stop. If the CPU 2 is executing an instruction for some reason, the CPU 2 stops executing the instruction after the currently executing instruction (in this example, instruction E) is completed. Therefore, from this point on, the CPU 2 (software) of the active system 1 does not operate on the various input/output devices shared by the system. After this, the CPU 52 (software) of the standby thread 51
Executes an instruction to instruct OI to switch systems, and 5W1
Each push-in/output device 103 to 108 connected to 02 can be connected to the standby system, and business can be restarted in the standby system.

FIG. 6 is a diagram showing an embodiment for carrying out the method of the present invention. In the figure, only the parts related to the present invention are shown, and other components necessary for a general information processing device (
For example, storage devices, arithmetic units, etc.) are omitted. In the figure, intersystem interface lines 111 to 114 are an SVP interrupt line to the standby system, an SVP interrupt signal line from the standby system, a forced stop signal line to the standby system, and a forced stop signal line from the standby system, respectively. .

In this embodiment, a holding circuit 201 temporarily holds the 8VP interrupt signal line 112, a masking circuit 202 masks the 8VP interrupt (disables reception), and an AND (logical product) of the outputs from the % holding circuit 201 and the masking circuit 202. ) A that generates the condition
ND circuit 203, other interrupt signal line group 2071 0'#L circuit 2 that generates an OR (logical sum) condition for each German interrupt signal line
04. An interrupt generation circuit 205 that is activated by the output of the OR circuit 204 and generates an interrupt to software, and a holding circuit 21 that temporarily holds the forced stop signal line 114 from the standby system.
1. An OR circuit 212 that generates an OR condition for other instruction stop signal line groups 214 and various instruction stop signal lines. OR circuit 212
an instruction stop control circuit 213 that is activated by the output of , and stops execution of the instruction at the end of the currently executing instruction; and an instruction register 22 that stores one word of the instruction to be executed by the software.
1. Decoder 22 that decodes the contents of the instruction register 221
2. A holding circuit 223 that temporarily holds the output signal when the decoder 222 decodes the svp interrupt generation instruction. S
8VP that generates output when a VP failure or CPU failure occurs
Interrupt generation circuit 225°, AND circuit 226° that generates an AND condition for the outputs of the holding circuit 223 and the SVP interrupt generation circuit 225, and a holding circuit 224 that temporarily holds the output signal when the decoder 222 decodes the forced stop instruction command. It is equipped with

Figure 6 shows the active system, but is the configuration the same for the standby system? shall have it.

In the active system, circuit 225 generates an output signal if the CPU or 8VP fails. If the software is at fault, the software executes an 8VP interrupt generation instruction, and the decoder 222 decodes this instruction to set the holding circuit 223. In either case, an 8VP interrupt signal is sent to the standby system via line 111.

On the other hand, considering FIG. 6 as a standby system, when an SVP interrupt occurs via the signal line 112, this interrupts the holding circuit 201.
The mask bit of the mask circuit 202 is held at t'0.
'', an interrupt signal of 75°C is generated from the AND circuit 203, and the 1st interrupt generation circuit 205 notifies the software of the interrupt.The software investigates the cause of the interrupt, and when it recognizes the SVP interrupt, prepares for system switching. In order to forcibly stop the active system, a forced stop instruction command (SYC command (I2=15
)). Decoder 222 decodes this instruction.

The result is temporarily held in the holding circuit 224, and a forced stop is instructed to the active system via the signal line 113.

If we consider the diagram in FIG. 6 as the active system, when a forced stop is instructed from the active standby system via the signal line 114, it is temporarily held in the holding circuit 211 and sent to the instruction stop control circuit 213 via the OR circuit 212. is output to. This circuit 213 interrupts and stops execution of the next and subsequent instructions at the end of the currently executed instruction.

As a result of the operations described above, when a system switch is required to remove harm from the active system, even if the active system is continuing instructions, the system can be safely switched and interrupted by stopping the commands on the active system. Business can be resumed.

As described above, the present invention has the advantage that thread switching operation can be easily guaranteed by adding a small amount of nodeware.

[Brief explanation of drawings]

Fig. 1 is a conceptual diagram of a duplex system, Fig. 2 is a block diagram showing an example of a duplex system, Fig. 3 is a block diagram showing intersystem interface signal lines of a duplex system according to the method of the present invention, and Fig. 4 is a block diagram showing an example of a duplex system. FIG. M5 is a time chart showing the operation according to the method of the present invention, and FIG. 6 is a block diagram showing an embodiment for carrying out the method of the present invention. In the figure, 1...current system, 2,53...
... central processing unit, 3.52 ... main memory,
4.55...Input/output control device, 5.54・River・
・Communication control device, 6.56...Monitoring device, 10
．． 60...System bus, 20, 30, 40
,70,80,90,120°130.140,150
,160,170・old・・signal line, 110~114・・
...Intersystem interface signal line, 1o1...
- Switching control device, 102...Switching device, 103
~108... Input/output equipment, 201, 211, 2
23, 224...Holding circuit, 202...
-Mask circuit, 203°226-...-AND circuit, 204,212-4-OR circuit, 205°...
...Interrupt generation circuit, 213...Instruction stop control circuit, 221...Register, 222...
decoder. <2/ Figure 1 Figure 5 Figure 6

Claims (1)

[Claims] In a system switching control method for an information processing system having a first and a second processing system, the first (or second) processing system responds to failure detection in the first (or second) processing system. sends an interrupt signal to the second (or first) processing system, and in response to the interrupt signal, the second (or first) processing system executes the first (or second) processing. After sending a forced stop signal to the system to stop the instruction execution operation of the first (or second) processing system, the second (or first) processing system A system switching control method for an information processing system, characterized in that processing of a processing system continues.