JPH053016B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an information processing device, and particularly to a microprogram control unit and a hardware control unit that interrupts the microprogram control unit and operates according to instructions from the microprogram control unit. The present invention relates to an information processing device configured to include the following.

[Conventional technology]

In recent years, the number of information processing devices using microprogram control has been increasing, and one type of device that uses microprogram control is a microprogram control unit that interrupts the microprogram control unit and operates according to instructions from the microprogram control unit. There is a device that has a hardware control unit that performs the following operations.

The hardware control unit usually performs processing based on its own judgment, but when the microprogram control unit needs to make a decision or process, it sends information to the microprogram control unit in the form of an interrupt to determine the type of interrupt. The interrupt request is raised along with the interrupt request, and the operation is suspended until support is received from the microprogram control unit. On the other hand, the microprogram control section determines what is the cause of the interrupt in the hardware control section, and issues an instruction to the hardware control section according to the interrupt. In the hardware control section,
Processing is restarted in response to an instruction from the microprogram control unit, and continues until judgment and processing by the microprogram control unit are required again.

[Problem that the invention seeks to solve]

In the conventional information processing apparatus described above, even if the hardware control section raises an erroneous interrupt request due to a failure or the like, the microprogram control section gives an operation instruction for the raised interrupt request.

However, if an interrupt request is raised by mistake due to a malfunction or other cause, the interrupt cause will not be reset even if the microprogram control section issues an operation instruction to the hardware control section, and the same interrupt request will be repeated. However, there was a problem in that other processing executed by the microprogram control unit was inhibited. Further, there is a problem in that the inside of the hardware control section changes depending on the operation instructions from the microprogram control section, which complicates failure analysis of the hardware control section.

[Means for solving problems]

The device of the present invention includes a microprogram control unit, outputs an interrupt request consisting of an interrupt request signal and specific information specifying the interrupt to the microprogram control unit, and responds to an operation instruction corresponding to the interrupt request supplied from the microprogram control unit. An interrupt request that generates the interrupt request signal in response to the occurrence of any one of a plurality of interrupt factors whose occurrence order is known in advance in an information processing device configured with a hardware control unit that operates in response. signal generating means;
a prediction signal generating means for generating a prediction signal corresponding to an interrupt factor predicted to occur next in response to the supply of the specific information; and a prediction signal generating means provided for each of the interrupt factors for supplying the corresponding prediction signal. predicted coincidence signal generation means for generating a predicted coincidence signal when the generated interrupt factor is predicted; and an interrupt factor that generates the specific information for specifying the generated interrupt factor in response to the predicted coincidence signal. and identifying means.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The information processing device shown in FIG. 1 includes a hardware control section 1 and a microprogram control section 2.
AND circuits 14 to 16 corresponding to each of ~c
, an interrupt permission circuit 13 , an OR circuit 17 , an encoder 18 , a flip-flop 19 , and a register 20 .

An interrupt request signal 60 and interrupt parameters 30, 31 are sent from the hardware control section 1 to the microprogram control section 2, and an instruction signal 70 and instruction parameters 71 are sent from the microprogram control section 2 to the hardware control section 1. Ru.

Figure 2 shows the interrupt factor a of the hardware control unit 1.
It is a diagram showing the order of occurrence of ~c. In FIG. 2, interrupt factor a or b occurs next to interrupt factor a, interrupt factor c occurs after interrupt factor b, and interrupt factor a occurs after interrupt factor c. A combination other than this, for example, an interrupt in which interrupt factor a is followed by interrupt factor c does not occur under normal conditions.

FIG. 3 is a diagram showing the relationship between the input and output of the encoder 18. In Fig. 3, the signal line 35
is “1”, the output of the encoder 18 (signal line 3
8, 39) becomes "11", indicating that the interrupt factor a has been turned on. When the signal line 35 is "0" and the signal line 36 is "1", the output of the encoder 18 becomes "10", indicating that the interrupt factor b is turned on. When the signal lines 35 and 36 are "0" and the signal line 37 is "1", the output of the encoder 18 becomes "01", indicating that the interrupt factor c is turned on. When the signal lines 35, 36, and 37 are all "0", the encoder 18 output becomes "00", indicating that the interrupt is an error interrupt.

FIG. 4 is a diagram showing the relationship between the input and output of the interrupt permission circuit 13. In FIG. 4, an interrupt parameter 3 which is an input of the interrupt enable circuit 13
When 0 and 31 are "11", the output of the interrupt permission circuit 13 (signal lines 32, 33, and 34) becomes "110". This indicates that the previous interrupt was interrupt factor a, and the next predicted interrupt is either interrupt factor a or interrupt factor b. When interrupt parameters 30 and 31 are “10”, interrupt enable circuit 1
The output of 3 becomes "001", indicating that the previous interrupt was the interrupt factor b, and the next predicted interrupt is the interrupt factor c. Furthermore, when interrupt parameters 30 and 31 are “01”, interrupt enable circuit 1
The output of 3 becomes "100", indicating that the previous interrupt was interrupt factor c, and the next predicted interrupt is interrupt factor a, and the interrupt parameter 3
When 0 and 31 are "00", the output of the interrupt enable circuit 13 becomes "000", indicating that the previous interrupt was an error interrupt and that all subsequent interrupts will be suppressed.

Assuming that the value "11" is currently held in the register 20 of the hardware control unit 1, the output of the interrupt permission circuit 13 is "110". When interrupt factor a turns on in this state, interrupt factor a passes through OR circuit 17 to flip-flop 1.
9 is set, and the output data of the encoder 18 (signal lines 38, 39) is taken into the register 20. At this time, the encoder 18 detects the interrupt factor a and the signal line 3.
Since the signal line 35 which is the AND result of 2 is "1", data "11" indicating that the interrupt is the interrupt factor a is output. When the flip-flop 19 is set, the interrupt request signal 60 is turned on, and the hardware control section 1 stops operating until an instruction from the microprogram control section 2 is received. At this time, the contents of the flip-flop 19 are held until the interrupt is accepted, and the contents of the register 20 are held until the next interrupt occurs.

When the microprogram control unit 2 receives an interrupt, it knows that it is an interrupt caused by interrupt cause a because the interrupt parameters 30 and 31 are "11", and sends an instruction for this interrupt to the instruction signal 7.
0, through instruction parameter 71. Upon receiving this instruction, the hardware control section 1 resumes the stopped operation and starts moving again.

After that, the hardware control unit 1 detects the interrupt cause c.
Suppose that the switch is turned on due to a malfunction or other reason. The interrupt factor c sets the flip-flop 19 through the OR circuit 17, and sets the encoder 1 in the register 20.
8 output data (signal lines 38, 39). At this time, the output data of the encoder 18 is "00" indicating an error interrupt. This is the value “11” when interrupt factor a occurs in register 20.
is held, the interrupt enable circuit 13 outputs "0" to the signal line 34, and the interrupt cause c
This is because the signal line 37 does not become "1" even if it is turned on.

When the microprogram control unit 2 receives an error interrupt whose interrupt parameters 30 and 31 are "00," it learns that the hardware control unit 1 is in a failure state, and after collecting data from the hardware control unit 1, It is possible to take measures against the failure, such as disconnecting the hardware control unit 1.

As described above, in this embodiment, all interrupt factors other than predicted interrupt causes can be reported to the microprogram control section 2 as error interrupts, and the microprogram control section 2 can then take appropriate measures.

〔Effect of the invention〕

As explained above, the present invention detects failures in the hardware control unit early by converting all interrupts other than predicted interrupts into error interrupts and notifying the microprogram control unit. This has the effect of facilitating analysis and preventing interference with other processing executed by the microprogram control section.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
2 is a diagram showing the order in which interrupt factors occur in the hardware control unit 1, FIG. 3 is a diagram showing the relationship between the input and output of the encoder 18, and FIG. 4 is a diagram showing the interrupt enable circuit 1.
FIG. 3 is a relationship diagram between input and output of No. 3; 1...Hardware control unit, 2...Microprogram control unit, 13...Interrupt permission circuit, 14
~16...AND circuit, 17...OR circuit, 18
... Encoder, 19 ... Flip-flop, 2
0...Register, 30, 31...Interrupt parameter, 60...Interrupt request signal, 70...Instruction signal,
71...Instruction parameters, 32-39...Signal lines, a, b, c...Interrupt factors.

Claims (1)

[Scope of Claims] 1. A microprogram control unit, which outputs an interrupt request consisting of an interrupt request signal and specific information specifying the interrupt, and provides an operation instruction corresponding to the interrupt request supplied from the microprogram control unit. and a hardware control unit that operates in response to an interrupt that generates the interrupt request signal in response to the occurrence of any one of a plurality of interrupt factors whose occurrence order is known in advance. request signal generation means; prediction signal generation means for generating a prediction signal corresponding to an interrupt factor that is predicted to occur next in response to the supply of the specific information; prediction matching signal generating means for generating a prediction matching signal when the interrupt factor that has occurred in response to the prediction signal being supplied is the predicted one; An information processing device comprising: interrupt factor identification means that generates information.