JP4554402B2 - Microcomputer with built-in interrupt controller - Google Patents

Description

  The present invention relates to a microcomputer incorporating an interrupt controller, and more particularly to a microcomputer incorporating an interrupt controller for managing the interrupt order of function macros.

  The microcomputer incorporates peripheral resources composed of macros having various functions, and manages and controls the operations of these peripheral resources. The basic configuration is that the CPU controls the activation of the function macro, which is a peripheral resource, notifies the CPU of an interrupt signal when the function macro completes its processing, and responds to the interrupt signal. The CPU executes necessary interrupt processing.

  If an interrupt signal to the CPU is generated at a high frequency, the CPU must perform an interrupt process such as saving the processing state being executed every time an interrupt occurs, which is not preferable because the overhead associated with the occurrence of the interrupt increases. . Therefore, an interrupt controller that monitors interrupt notifications from multiple function macros, executes the minimum necessary processing when receiving an interrupt notification, and notifies the CPU of an interrupt signal when multiple interrupt notifications are confirmed is provided. Has been proposed. For example, as described in Patent Document 1.

  FIG. 1 is a schematic configuration diagram of a conventional microcomputer described in Patent Document 1. In FIG. In this example, the microcomputer MCON is supplied with some signal S10 from the external device 10, and functions macros A, B, and C for processing the signal S10 serially and a memory for outputting processed data Sc to the external memory 14. And a controller 13. These function macros A, B, and C and the memory controller 13 are connected to the CPU 12 via the internal bus BUS. The function macro A processes the signal S10, the processed signal Sa is processed by the function macro B, the processed signal Sb is processed by the function macro C, and the processed signal Sc is stored in the external memory 14. Is done.

Further, the microcomputer MCON receives the interrupt signals IRa, IRb, IRc from the function macro in order to reduce the frequency of interrupts to the CPU 12, and outputs an interrupt signal IRx to the CPU 12 when all interrupt signals are received. It has a controller 11. The interrupt controller 11 outputs an interrupt signal to the CPU at the stage when the interrupt signals from each function macro are gathered, and prevents the CPU 12 from being disturbed each time by the interrupt signal from each function macro.
JP 2000-236688 A

  Since the conventional interrupt controller outputs the interrupt signal to the CPU after confirming the generation of a plurality of interrupt signals, the overhead associated with the CPU interrupt generation is reduced. However, if all three interrupt signals IRa, IRb, and IRc are received, the interrupt controller 11 outputs the interrupt signal IRx to the CPU 12, so that the interrupt signals IRa, IRb, and IRc are received in an order that is not normal for some reason. Even in this case, the interrupt controller 11 outputs the interrupt signal IRx to the CPU 12.

  There are various possible causes for the occurrence of interrupt signals in an abnormal order. One of them is a bug in the function macro hardware or a bug in the program executed by the CPU. Cases can be considered. In some cases, it may be considered that interrupt signals are generated in an abnormal order due to the occurrence of noise. In this way, it is desirable to be able to issue an abnormal interrupt to the CPU when the order of interrupts is increased for some reason.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a microcomputer that determines whether or not a plurality of interrupt signals are normally generated and issues a CPU interrupt.

  In order to achieve the above object, according to a first aspect of the present invention, there is provided a micro processing unit comprising a central processing unit, a plurality of function macros, and an internal bus connecting the central processing unit and the plurality of function macros. In the computer, an interrupt controller that receives a first interrupt signal from each of the plurality of function macros and outputs a second interrupt signal to the central processing unit when the plurality of first interrupt signals are generated in a predetermined order. It is characterized by having.

  According to the first aspect, the interrupt controller outputs interrupt signals to the central processing unit when interrupt signals from a plurality of function macros are received in a normal order. When the first interrupt signal is received, the state is detected and processing different from normal processing can be performed.

  In the first aspect, in a preferred embodiment, when the plurality of first interrupt signals are generated in the predetermined order, the interrupt controller stores a normal interrupt factor in an interrupt factor register and stores the central processing unit. The second interrupt signal is output to the central processing unit and the abnormal interrupt factor is stored in the interrupt factor register when the plurality of first interrupt signals are not generated in a predetermined order. Output a signal.

  According to this embodiment, the interrupt controller incorporates an interrupt factor register, stores normal interrupt factor information and abnormal interrupt factor information in the register, and outputs a second interrupt signal to the central processing unit. Therefore, when the central processing unit receives the second interrupt signal, the central processing unit can distinguish between a normal interrupt and an abnormal interrupt by checking the interrupt factor register, and can execute the corresponding processing. .

  In the first aspect, in a preferred embodiment, the interrupt controller includes an interrupt order setting register in which a predetermined order of the first interrupt signals is set, and the predetermined order of the order setting register is arbitrary. Can be set.

  In the first aspect, in a preferred embodiment, the interrupt controller activates one of the function macros in response to receiving the first interrupt signal. Instead of the central processing unit, the interrupt controller executes a start process for each function macro, thereby performing a process associated with the generation of an interrupt to the central processing unit.

  According to the present invention, the frequency of interrupts to the central processing unit is reduced, and a normal interrupt is issued only when the interrupt generation order of the functional units is normal, and an abnormal interrupt is issued when the interrupt generation order is abnormal. , It is possible to distinguish between functional unit operation errors.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof.

  FIG. 2 is a configuration diagram of the microcomputer according to the present embodiment. The present embodiment is an example of a microcomputer that performs image processing of a digital still camera. A camera module 10 is provided as an external device. The function macros A, B, and C constitute a camera interface, and the function macro A performs a clock change process for converting the image data VD supplied in the clock cycle of the camera module into a clock cycle in the microcomputer MCON. The function macro B performs image reduction processing for converting the image size captured by the camera module 10 into a display size of a monitor display device (not shown). By this image reduction process, the number of pixels is reduced. The function macro C then converts the YUV422 color data into YUV420 color data, or converts the line-sequential YUV data into the order of the color planes of the luminance component Y and the color difference component UV (plane sequential). Do.

  The image data Sc processed by the three function macros is stored in the external memory 14 via the memory controller 13.

  Processing of image data VD from the camera module 10 will be described below. The camera module 10 outputs the image data VD to the function macro A together with the synchronization signal Sync (for example, vertical and horizontal synchronization signals). The function macros A, B, and C have been activated in advance by an activation signal (not shown) from the CPU 12. The function macro A temporarily stores the image data VD in the buffer, reads it from the buffer in synchronization with the internal clock of the microcomputer MCON, and outputs it to the function macro B as the image data Sa. Thereby, a clock transfer process is performed. Further, the function macro A outputs the synchronization signal SyncA obtained by delaying the synchronization signal Sync for a predetermined time to the function macro B together with the image data Sa. The function macro A outputs the interrupt signal IRa when the clock transfer processing of the image data for one frame is completed.

  FIG. 2 shows a part of the internal configuration of the function macro A. In the function macro A, when “1” is written to any one of the processing unit 17 that performs the clock transfer process, the interrupt register IRReg in which the interrupt factor information from the processing unit is written, and flags R1 to R4 of the interrupt register. An OR gate 16 for outputting an interrupt signal IRa. When the processing of the image data for one frame is completed, the processing unit 17 writes the flag “1” in the corresponding area of the interrupt register IRReg. When the flag “1” is written to the interrupt register IRReg, the OR gate 16 outputs the interrupt signal IRa of the function macro A. Further, the function macro A stores any abnormality that occurs in the interrupt register IRReg as an abnormal interrupt flag. In response to this, an interrupt signal IRa is output.

  The function macros B and C have the same internal configuration. As described above, when an interrupt event occurs according to internal processing, the function macros A, B, and C write the flag “1” in the interrupt register area corresponding to the event. As a result, the interrupt signal IRa is automatically output. Also, when any abnormality occurs, an abnormal interrupt flag may be written to the interrupt register and an interrupt signal may be output.

  When the function macro A completes processing of one frame of image data, it outputs an interrupt signal IRa. The interrupt controller 11 receives this interrupt signal IRa. The interrupt controller 11 can check the interrupt register IRReg in the function macro A to identify whether it is a normal interrupt or an abnormal interrupt.

  The function macro B inputs the processed signal Sa from the function macro A together with the synchronization signal SyncA, and performs the above-described image reduction process. When the image reduction process for one frame is completed, as in the case of the function macro A, the normal end flag “1” is written to the interrupt register in the function macro B, and the interrupt signal IRb is output. In response to the interrupt signal IRb, the interrupt controller 11 checks the interrupt register in the function macro B to confirm whether it is a normal interrupt or an abnormal interrupt.

  Finally, the function macro C receives the processed signal Sb from the function macro B together with the synchronization signal SyncB, and performs the above-described format conversion process. When the format conversion process for one frame is completed, the processed image data Sc is stored in the external memory 14 via the memory controller 13. When the transfer to the external memory 14 is completed, the function macro C outputs the interrupt signal IRc like the other macros.

  FIG. 3 is a configuration diagram of the interrupt controller in the present embodiment. The interrupt controller 11 according to the present embodiment includes an interrupt determination unit 112 that receives interrupt signals IRa, IRb, and IRc and outputs the interrupt signal IRx to the CPU 12, an interrupt order setting register 110, and an interrupt factor register 114. . The interrupt determination unit 112 is a kind of state machine, and the state is changed by interrupt signals IRa, IRb, and IRc from the function macros A, B, and C. The interrupt order setting register 110 is a register for setting the order of interrupt signals during normal operation, and can be set from the outside via the CPU 12, for example.

  When the interrupt determination unit 112 receives the interrupt signals IRa, IRb, and IRc in the order set in the interrupt order setting register 110, the interrupt determination unit 112 issues a normal interrupt to the CPU 12, but when the interrupt signals are received in an order other than the order, , Issue an abnormal interrupt. The interrupt factor register 114 is a register that stores a flag according to the interrupt factor when the interrupt signal IRx is output. For example, when the interrupt signals are received in the normal interrupt order that has been set, the interrupt factor is a normal end. On the other hand, when the interrupt signals are received in an order different from the interrupt order, the interrupt factor is an abnormality. The interrupt determination unit 112 writes a normal or abnormal interrupt factor flag in the interrupt factor register 114 and outputs an interrupt request signal IRx to the CPU 12. In response to this, the CPU 12 reads the interrupt factor register 114 via the signal 20 and determines whether the interrupt request signal IRx is a normal interrupt or an abnormal interrupt. In particular, in the case of an abnormal interrupt factor, information about which function macro is abnormal is also written to the interrupt factor register 114. Therefore, the CPU 12 can identify which function macro has an abnormality.

  FIG. 4 is a state transition diagram of the interrupt determination unit. The states C1 to C6 are transferred to the illustrated state in accordance with each occurrence event. The start state C1 unconditionally transits to an interrupt wait state C2 from the function macro A. In normal operation, processing is performed in the order of the function macros A, B, and C. Therefore, when the interrupt signal IRa from the function macro A is received in the state C2, the state transits to the interrupt waiting state C3 from the function macro B. When the interrupt signal IRb from the function macro B is received in the state C3, the state transits to the interrupt wait state C4 from the function macro C, and when the interrupt signal IRc from the function macro C is further received in the state C4, the CPU is normal. Transition to state C5 for issuing an interrupt. When the interrupt determination unit 112 stores the normal interrupt flag in the interrupt factor register and outputs the interrupt signal IRx, the interrupt determination unit 112 transits to the state C2. The CPU 12 identifies a normal interrupt by checking the interrupt factor register 114 via the signal 20.

  When interrupt signals are received in an order different from the order of the normal processing, the interrupt determination unit 112 issues an abnormal interrupt to the CPU 12. That is, when the interrupt signals IRb and IRc are received from the function macro B or C in the state C2, the state transits to the abnormal interrupt issue state C6. Similarly, when the interrupt signals IRc and IRa are received in the state C3 and when the interrupt signals IRa and ORb are received in the state C4, both transition to the abnormal interrupt issue state C6. In the abnormal interrupt issuance state, the interrupt determination unit 112 writes an abnormal interrupt factor flag in the interrupt factor register 114 and issues an interrupt request signal IRx to the CPU 12. The interrupt factor register 114 has, for example, an abnormality flag area for each function macro, and an abnormality flag is stored in an area corresponding to the function macro that has generated an interrupt signal in an abnormal order. The CPU 12 recognizes an abnormal interrupt by checking the interrupt factor register 114 in response to the interrupt request signal IRx. Also, which function macro is in an abnormal state is identified depending on which region has an abnormal flag.

  When the CPU 12 recognizes a normal interrupt, it clears the interrupt register IRReg in the function macros A, B, and C via the internal bus BUS. As a result, the interrupt states of the function macros A, B, and C are released. In addition, since the camera interface composed of the function macros A, B, and C is in a state in which the image data VD for one frame from the camera module is stored in the external memory 14, the CPU 12 thereafter processes the image data in the external memory 14. Predetermined image processing. For example, the image processing includes JPEG encoding, MPEG encoding, display processing on a monitor display device, and the like.

  When the CPU 12 recognizes the abnormal interrupt, it resets the function macro in which the abnormality has occurred and returns it to the initial state. Also, processing according to the cause of the abnormality is executed. For example, the interrupt register of each function macro is cleared and the interrupt factor register 114 of the interrupt controller 11 is cleared.

  As described above, since the interrupt controller 11 is provided, the CPU 12 is not disturbed each time by the interrupt signals IRa, IRb, IRc from the function macros A, B, C, and the interrupt signal is received. Interrupt processing such as job saving during execution by the CPU can be reduced. The interrupt controller 11 checks whether or not the interrupt signals from the function macro are received in a normal order. If the interrupt signals are received in the normal order, the interrupt controller 11 can issue a normal interrupt and receive it in an abnormal order. If this happens, an abnormal interrupt can be issued. Therefore, when the order of interrupt signals is different from normal due to a hardware bug or software bug, the interrupt controller 11 can detect it and issue an abnormal interrupt to the CPU 12.

  FIG. 5 is a configuration diagram of the microcomputer according to the second embodiment. This microcomputer MCON is a digital still camera control computer as in the above-described embodiment, and has three function macros A, B, and C as peripheral resources. The microcomputer MCON is connected to the camera module 10 which is an external device and an external memory 14. In this embodiment, the function macro A corresponds to the camera interface composed of the function macros A, B, and C in FIG. A process of converting the data to the external memory 14 is performed. The function macro B reads the image data in the external memory 14, rotates the image by 90 degrees, and stores the image data in the external memory 14 again. The function macro C reads the image data stored in the external memory 14 and outputs it to the monitor display device 15 comprising a liquid crystal display device for display. In other words, the microcomputer MCON continues to display the image data captured by the camera module 10 on the monitor display device 15 by performing image processing for each frame. When an event occurs such as when the shutter is pressed in the camera module 10, the frame image at that time is recorded in the external memory 14 as shooting data.

  Also in this embodiment, each of the function macros A, B, and C has the interrupt register IRReg and the OR circuit 16 as shown in FIG. 2, and the interrupt flag “1” is written in the interrupt register within the function macro. Interrupt signals IRa, IRb, IRc are output. Further, the interrupt controller 11 monitors reception of interrupt signals from each function macro in a normal order and reception in an abnormal order, and issues a normal interrupt or an abnormal interrupt to the CPU 12. In this embodiment, when the interrupt controller 11 receives interrupt signals in the normal order for each function macro, the interrupt controller 11 outputs start signals INb and INc for starting the function macro for performing the next processing. That is, when the interrupt signal IRa is received, the interrupt controller 11 outputs the activation signal INb to the function macro B to activate it. Similarly, when the interrupt signal IRb is received, the activation signal INc is output to the function macro C to be activated. When receiving the interrupt signal IRc, the interrupt controller 11 issues a normal interrupt to the CPU 12. In response to this, the CPU 12 outputs an activation signal INa to the function macro A. Furthermore, when the interrupt controller 11 receives interrupt signals in an abnormal order, it issues an abnormal interrupt to the CPU 12 without outputting the start signal.

  FIG. 6 is a configuration diagram of the interrupt controller according to the second embodiment. Similarly to FIG. 3, the interrupt controller 11 also receives the interrupt signals IRa, IRb, IRc and outputs the interrupt signal IRx to the CPU 12, an interrupt order setting register 110, an interrupt factor register 114, Have The interrupt determination unit 112 is a kind of state machine, and the internal state is changed by interrupt signals IRa, IRb, IRc from the function macros A, B, C. The interrupt order setting register 110 is a register for setting the order of interrupt signals during normal operation, and can be set from the outside via the CPU 12, for example. Further, the interrupt controller 11 has a macro activation control unit 116, and the macro activation control unit 116 outputs corresponding activation signals INb and INc in response to the interrupt signals IRa and IRb.

  As in FIG. 3, when the interrupt determination unit 112 receives the interrupt signals IRa, IRb, IRc in the order set in the interrupt order setting register 110, it issues a normal interrupt, but in an order other than that order. If received, issue an abnormal interrupt. The interrupt factor register 114 is a register that stores a flag according to the interrupt factor when the interrupt signal IRx is output. The interrupt determination unit 112 sets a normal or abnormal factor flag in the interrupt factor register 114. In addition to writing, an interrupt request signal IRx is output to the CPU 12. In response to this, the CPU 12 reads the interrupt factor register 114 via the signal line 20 and determines whether the interrupt request signal IRx is a normal interrupt or an abnormal interrupt.

  FIG. 7 is a state transition diagram of the interrupt determination unit. First, a transition is made from the start state C10 to the interrupt wait state C11 from the function macro A. In normal processing, the state C11 transitions to the states C12, C13, C14, C15, and C16. In the abnormal process, an unscheduled interrupt signal is received from the interrupt wait states C11, C13, C15, and the state transitions to state C17. Hereinafter, it demonstrates in order.

  First, in the function macro interrupt waiting state C11, when the function macro A activated by the CPU 12 completes transferring one frame of image data from the camera module 10 to the external memory 14, the interrupt signal IRa is output. The interrupt determination unit 112 makes a transition from the state C11 to the state C12 that activates the function macro B in response to reception of the interrupt signal IRa. In this state, the interrupt determination unit 112 causes the macro activation control unit 116 to output an activation signal INb. Then, the state transits to the interrupt waiting state C13 from the function macro B.

  Next, when the function macro B is activated to complete the image rotation process and store it in the external memory 14, an interrupt signal IRb is output. The interrupt determination unit 112 transitions to a state C14 in which the function macro C is activated in response to the interrupt signal IRb. Then, the macro activation control unit 116 is caused to output the activation signal INc, and the state transitions to the state C15. In the state C15, when the function macro C is activated and the LCD control for reading one frame of image data from the external memory 14 and displaying it on the monitor display device is completed, the interrupt signal IRc is output, and the interrupt determination unit 112 Transition to state C16 to issue. In state C16, the interrupt determination unit 112 writes a normal interrupt flag to the interrupt factor register 114, outputs an interrupt request signal IRx to the CPU 12, and transitions to state C11. The CPU 12 checks the interrupt factor register 114 in response to the interrupt request signal IRx, and when it recognizes that it is a normal interrupt, it clears the interrupt registers in all function macros A, B, and C via the internal bus BUS. Then, the start signal INa is output to the function macro A. Further, the CPU 12 clears the interrupt factor register 114 of the interrupt controller 11 via the signal 20.

  When the interrupt determination unit 112 receives an interrupt signal different from the normal order in the states C11, C13, and C15, the interrupt determination unit 112 transitions to an abnormal interrupt issue state C17. Then, the interrupt determination unit 112 stores an abnormality flag in the interrupt factor register 114 and outputs an interrupt request signal IRx to the CPU 12. In response to the interrupt request signal IRx, the CPU 12 detects an abnormal flag in the interrupt factor register 114 and recognizes an abnormal interrupt. When an abnormal interrupt occurs, the CPU 12 clears the interrupt register of each function macro and resets the function macro that has output the interrupt signal in an abnormal order. Also, the interrupt factor register 114 is cleared.

  The interrupt factor register 114 has an abnormality flag area corresponding to the function macro. When the interrupt determination unit 112 receives interrupt signals in an abnormal order, the interrupt determination unit 112 writes an abnormality flag in the abnormality flag area of the corresponding function macro. The CPU 12 can identify which function macro has an abnormality.

  In the second embodiment, since the interrupt controller 11 issues a normal interrupt to the CPU when receiving the interrupt signals in a normal order, the CPU receives the interrupt signal frequently and is disturbed. Can be reduced. Further, the interrupt controller 11 can issue an abnormal interrupt to the CPU when receiving the interrupt signals in an abnormal order. Further, when the interrupt controller 11 receives an interrupt signal from each function macro in a normal order, the interrupt controller 11 activates a function macro to be processed next. Therefore, the burden on the CPU can be reduced accordingly.

  In the two embodiments described above, the interrupt controller 11 monitors whether or not the interrupt signals from the three function macros are in a normal order, and issues an abnormal interrupt to the CPU if the order is abnormal. Further, the interrupt controller 11 may check an interrupt register in each function macro in response to an interrupt signal from each function macro to confirm whether it is a normal interrupt or an abnormal interrupt. In that case, when it is detected that the interrupt is abnormal, an abnormal interrupt is issued to the CPU. In this case, the interrupt determination unit 112 stores a flag indicating an abnormal interrupt from the corresponding function macro in a corresponding area of the interrupt factor register 114, and outputs an interrupt request signal IRx to the CPU 12. The CPU 12 checks the interrupt factor register 114, recognizes the function macro subject to the abnormal interrupt, and resets the function macro.

  The above embodiment is summarized as follows.

(Supplementary note 1) In a microcomputer having a central processing unit, a plurality of function macros, and an internal bus connecting the central processing unit and the plurality of function macros,
An interrupt controller that receives a first interrupt signal from each of the plurality of function macros and outputs a second interrupt signal to the central processing unit when the plurality of first interrupt signals are generated in a predetermined order; A microcomputer characterized by.

(Appendix 2) In Appendix 1,
When the plurality of first interrupt signals are generated in the predetermined order, the interrupt controller stores a normal interrupt factor in an interrupt factor register and outputs the second interrupt signal to the central processing unit. A microcomputer characterized in that when a plurality of first interrupt signals are not generated in a predetermined order, an abnormal interrupt factor is stored in the interrupt factor register and the second interrupt signal is output to the central processing unit.

(Appendix 3) In Appendix 2,
In response to the second interrupt signal, the central processing unit reads the information in the interrupt factor register, performs the corresponding interrupt processing when the information is a normal interrupt factor, and responds when the information is an abnormal interrupt factor. A microcomputer characterized by resetting a function macro.

(Appendix 4) In Appendix 1,
The microcomputer according to claim 1, wherein the interrupt controller includes an interrupt order setting register in which a predetermined order of the first interrupt signal is set, and the predetermined order of the order setting register can be arbitrarily set.

(Appendix 5) In Appendix 1,
The microcomputer, wherein the interrupt controller activates one of the function macros in response to reception of the first interrupt signal.

(Appendix 6) In Appendix 1,
In response to an interrupt signal from the function macro, the interrupt controller reads the interrupt register in the function macro, and in the case of an abnormal interrupt, stores the abnormal interrupt factor in the interrupt factor register and stores it in the central processing unit. A microcomputer which outputs an interrupt signal of 2.

(Appendix 7) In Appendix 1,
The plurality of function macros include a first function macro that outputs image data supplied from an external camera module at the timing of an internal clock, and a second function that reduces the image data from the first function macro. A macro, and a third function macro that performs format conversion processing for converting image data from the second function macro into a display device format,
The microcomputer according to any one of claims 1 to 3, wherein each of the first to third function macros outputs an interrupt signal to the interrupt controller when image data for one frame is processed.

(Appendix 8) In Appendix 1,
The plurality of function macros include a first function macro that converts image data supplied from an external camera module into a predetermined size and stores the image data in an external memory, and an external memory converted by the first function macro. A second function macro for performing image rotation processing on image data and storing the image data in the external memory; and a third function macro for outputting image data in the external memory subjected to image rotation processing by the second function macro to a display device; Have
The microcomputer according to any one of claims 1 to 3, wherein each of the first to third function macros outputs an interrupt signal to the interrupt controller when image data for one frame is processed.

It is a schematic block diagram of the conventional microcomputer. It is a block diagram of the microcomputer in this Embodiment. It is a block diagram of the interrupt controller in this Embodiment. It is a state transition diagram of an interrupt determination unit. It is a block diagram of the microcomputer in 2nd Embodiment. It is a block diagram of the interrupt controller in 2nd Embodiment. It is a state transition diagram of an interrupt determination unit.

Explanation of symbols

MCON: microcomputer BUS: internal bus 11: interrupt controller 12: central processing unit 13: memory controller 14: external memory

Claims (4)

In a microcomputer having a central processing unit, a plurality of function macros, and an internal bus connecting the central processing unit and the plurality of function macros,
When a first interrupt signal is received from each of the plurality of function macros and the plurality of first interrupt signals are generated in a predetermined order, a normal interrupt factor is stored in an interrupt factor register and stored in the central processing unit. When the plurality of first interrupt signals are not generated in the predetermined order, an abnormal interrupt factor is stored in the interrupt factor register and the second interrupt signal is sent to the central processing unit. A microcomputer having an interrupt controller that outputs and activates a function macro to be processed next in response to reception of a first interrupt signal generated in the predetermined order . In claim 1,
In response to the second interrupt signal, the central processing unit reads the information in the interrupt factor register, performs the corresponding interrupt processing when the information is a normal interrupt factor, and responds when the information is an abnormal interrupt factor. A microcomputer characterized by resetting a function macro. In claim 1,
The microcomputer according to claim 1, wherein the interrupt controller includes an interrupt order setting register in which a predetermined order of the first interrupt signal is set, and the predetermined order of the order setting register can be arbitrarily set. In claim 1,
The interrupt controller outputs the second interrupt signal to the central processing unit without activating the function macro in response to receiving the first interrupt signal not in the predetermined order. Microcomputer.

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