JP4921582B2 - Image data transfer circuit - Google Patents

Description

  The present invention relates to an image data transfer circuit for fetching image data sent from a video camera or the like into an LSI (Large Scale Integrated circuit), and particularly to exception control when an error occurs.

  FIG. 2 is a block diagram of a conventional moving image processing LSI.

  The moving image processing LSI 1 performs image processing of the image data sent from the video camera 2 and stores it in the external memory 3, and then notifies the external host CPU (central processing unit) 4 that the image processing is completed. By doing so, the image data after image processing can be read out by the host CPU 4. The moving image processing LSI 1 includes a camera interface (hereinafter referred to as “I / F”) 10, an external memory I / F 20, an image processing engine 30, and a CPU I / F 40, which are connected via a common internal bus 50. To be connected.

The camera I / F 10 transfers the image data VDATA sent from the video camera 2 together with the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC to the external memory I / F 20 via the internal bus 50. The external memory I / F 20 writes the image data transferred from the camera I / F 10 to the external memory 3 and reads / writes image data from / to the external memory 3 based on a request from the image processing engine 30. The image data is read from the external memory 3 based on a request from the CPU I / F 40. The image processing engine 30 performs an encoding process on the image data written in the external memory 3 by the camera I / F 10 and stores the image data in the external memory 3 again. The CPU I / F 40 reads image data that has been subjected to encoding processing and the like from the external memory 3 and transfers it to the host CPU 4.

  The camera I / F 10 in the moving image processing LSI 1 includes an input unit 11, a filter 12, a FIFO (first-in first-out) buffer 13, and an output unit 14. The input unit 11 inputs the image data VDATA sent from the video camera 2 together with the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC, and indicates whether the image data signal VD and the image data signal VD are valid in units of pixels. This is output to the filter 12 together with the image data valid signal VA. Furthermore, the input unit 11 has an error detection function for detecting an abnormality in the image data VDATA. When an abnormality is detected, the input unit 11 outputs a stop request signal STP to the filter 12 and the output unit 14. ing.

The input unit 11, the filter 12, the FIFO buffer 13, and the output unit 14 are connected by a pipeline using the image data signal VD and the image data valid signal VA, and are connected from the output unit 14 via the internal bus 50. Image data is written to the external memory I / F 20.

  In the camera I / F 10, image data VDATA of the video camera 2 is input by a vertical synchronization signal VSYNC and a horizontal synchronization signal HSYNC. The input unit 11 takes in a period during which the two synchronization signals VSYNC and HSYNC are output as valid data. The input image data VDATA is propagated as an image data signal VD together with the image data valid signal VA along with the filter 12 and the FIFO buffer 13 in order by pipeline processing, and finally output from the output unit 14 to the internal bus 50.

  When the image data valid signal VA is output, the filter 12, the FIFO buffer 13, and the output unit 14 determine that new image data has been input, and process the image data signal VD. The pipeline processing is performed in synchronization with the image data valid signal VA given in units of pixels.

  When the input unit 11 detects an abnormality in the input image data VDATA, the input unit 11 outputs a stop request signal STP to the filter 12 and the output unit 14 in order to stop the capturing process of the frame including the image data. As a result, the pipeline processing being executed is stopped, the processing of frames including abnormal image data is stopped, and the use load of the internal bus 50 is reduced. The following documents are examples of conventional technical documents related to image data transfer.

JP-A-9-139828 Japanese Patent Laid-Open No. 11-202848

  However, the camera I / F 10 has the following problems.

That is, when the stop request signal STP is output due to an abnormality in the input image data VDATA, the pipeline processing in the input unit 11, the filter 12, and the output unit 14 is stopped. However, the transfer of the image data to the internal bus 50 by the output unit 14 may be prolonged depending on the load status of the internal bus 50. Therefore, when the stop request signal STP is output, the transfer of the image data of the previous normal frame may not be completed. In such a case, there is a problem that data transfer is stopped by the stop request signal STP, the image data of the normal frame is discarded, and the abnormal data of the previous frame affects the processing of the next frame .

  SUMMARY OF THE INVENTION An object of the present invention is to provide an image data transfer circuit that can perform an exceptional process without affecting normal frame image data when an error is detected in the image data.

The image data transfer circuit according to the present invention outputs an image data valid signal indicating in pixel units whether or not the image data given in accordance with the frame synchronization signal is valid, and when no abnormality is detected in the image data, a frame is added to the image data. An input processing unit that adds a start bit for displaying whether or not the first pixel is output as an image data signal and stops output of the image data signal when an abnormality in the image data is detected; The image data signal output from the input processing unit is sequentially stored in accordance with the image data valid signal, and the stored image data signal is read in the stored order in accordance with a read request, and the image data is output from the buffer. A signal is read out and transferred to the outside, and the scan of the read image data signal is performed. An output section being restarted by the start bit when the has been shown to be a first pixel of a frame by Tobitto, characterized by comprising.

When the input processing unit detects the start of a frame, the image data transfer circuit of the present invention adds a start bit indicating the start of the frame to the image data signal and outputs it to the subsequent stage. Each bit is transferred to the subsequent stage. As a result, when the output unit detects the start bit, it can be restarted and transfer data to the internal bus, so all of the normal frame image data stored in the buffer can be discarded without being discarded. There is an advantage that it can be transferred to the internal bus. In addition, since the filter and the output unit are restarted with a start bit given for each frame and process image data, there is an advantage that abnormal data of the previous frame does not have a possibility of affecting the processing of the next frame. Furthermore, the image data transfer circuit of the present invention has an advantage that the overall circuit configuration can be simplified, although the buffer capacity is increased by the start bit.

FIG. 1 is a configuration diagram of an image data transfer circuit showing a first embodiment of the present invention. FIG. 2 is a block diagram of a conventional moving image processing LSI. FIG. 3 is a configuration diagram of an image data transfer circuit showing the reference example 1 of the present invention. FIG. 4 is a signal waveform diagram showing the operation of the image data transfer circuit of FIG. Figure 5 is a signal waveform diagram representing an operation of the image data transfer circuit of FIG.

Modes for carrying out the present invention will become apparent from the following description of the preferred embodiments when read in light of the accompanying drawings. However, the drawings are only for explanation and do not limit the scope of the present invention.
[Reference Example 1]
(Configuration of Reference Example 1)
FIG. 3 is a configuration diagram of an image data transfer circuit showing the reference example 1 of the present invention.

  The image data transfer circuit 10A is provided in place of, for example, the camera I / F 10 in FIG. 2, and in addition to the input processing unit 11A, the filter 12, the FIFO buffer 13, and the output unit 14A, an input side frame counter 15 is provided. And a frame detection unit 16, an output side frame counter 17, a comparison unit 18, and a stop control unit 19.

  The input processing unit 11A receives image data VDATA sent from a video camera or the like in synchronization with the frame synchronization signal of the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC, and the image data signal VD1 This is output to the filter 12 together with the image data valid signal VA1 indicating whether it is valid or not in pixel units. Further, the input processing unit 11A outputs an error detection signal ERR to the stop control unit 19 when detecting an abnormality in the image data VDATA, and stops the subsequent input processing for the frame. Yes.

  The filter 12 performs a filtering process on the image data signal VD1 given from the input processing unit 11A as necessary, and gives the processed image data signal VD2 and the image data valid signal VA2 to the FIFO buffer 13. . The FIFO buffer 13 sequentially stores the image data signal VD2 given from the filter 12, and reads it as the image data signal VD3 in the stored order in accordance with a read request from the output unit 14A.

  The output unit 14A receives the image data valid signal VA3, reads the image data stored in the FIFO buffer 13, and outputs the image data signal VD4 to the internal bus. The output unit 14A further outputs a frame start pulse FP to the frame counter 17 every frame start of the read image data, and stops the operation when the stop request signal STP is given. Yes.

  The input processing unit 11A, the filter 12, the FIFO buffer 13, and the output unit 14A are connected by a pipeline using an image data signal VD and an image data valid signal VA. When the image data valid signal VA given to each pixel indicates a valid state (for example, level “H”), it is determined that new image data has been input, and the image data is synchronized with the image data valid signal VA. Pipeline processing of the data signal VD is performed.

  On the other hand, the frame counter 15 provided on the input side outputs the frame number FNO1 being currently input by counting up each time the vertical synchronization signal VSYNC rises. The frame number FNO1 is given to one input side of the comparison unit 18. The frame detection unit 16 gives a restart signal RST to the stop control unit 19 every time the vertical synchronization signal VSYNC rises.

  On the other hand, the frame counter 17 provided on the output side outputs the frame number FNO2 being currently output by counting the frame start pulse FP given from the output unit 14A. The frame number FNO2 is given to the other input side of the comparison unit 18. The comparison unit 18 compares the two frame numbers FNO1 and FNO2, and gives a match signal EQU to the stop control unit 19 when they match.

The stop control unit 19 determines whether or not the coincidence signal EQU is output from the comparison unit 18 when the error detection signal ERR is given from the input processing unit 11A, and while the coincidence signal EQU is not output. When the coincidence signal EQU is output without outputting the stop request signal STP, the stop request signal STP is output. The stop control unit 19 stops outputting the stop request signal STP when the restart signal RST is given from the frame detection unit 16.
(Operation of Reference Example 1 )
Figure 4 is a signal waveform diagram representing an operation of the image data transfer circuit of FIG. Hereinafter, with reference to FIG. 4, the operation of FIG.

  When the image data VDATA, the vertical synchronization signal VSYNC, and the horizontal synchronization signal HSYNC are input to the image data transfer circuit 10A from a video camera or the like, the input processing unit 11A outputs both the synchronization signals VSYNC and HSYNC. Capture period as valid data.

  The input processing unit 11A determines whether the input image data VDATA is normal. If the image data is normal, the input processing unit 11A outputs the image data signal VD1 to the filter 12 together with the image data valid signal VA1. At this time, the error detection signal ERR is not output. The image data is further propagated by pipeline processing in the order of the FIFO buffer 13 and the output unit 14A, and finally output from the output unit 14A to the internal bus.

  The filter 12, the FIFO buffer 13, and the output unit 14 determine that new image data has been input when the image data valid signals VA1, VA2, and VA3 indicate valid states (for example, level “H”). The data signal VD is processed. The pipeline processing is performed in synchronization with the image data valid signal VA given in units of pixels. At this time, the frame number FNO2 output from the output-side frame counter 17 is equal to or smaller than the frame number FNO1 output from the input-side frame counter 16. Further, since the error detection signal ERR is not output, the stop request signal STP from the stop control unit 19 is also not output.

When the input processing unit 11A detects an abnormality in the image data during the input processing of the image data VDATA with the frame number f2 at time t1 in FIG. 4 , the input processing unit 11A sends an error detection signal ERR to the stop control unit 19. Is output. At this time, when the output unit 14A reads the image data signal VD3 of the frame number f1 from the FIFO buffer 13, the value of the frame number FNO2 output from the frame counter 17 is f1. Accordingly, the coincidence signal EQU is not output from the comparison unit 18. Therefore, the stop request signal STP from the stop control unit 19 is not output, and the operations of the filter 12, the FIFO buffer 12, and the output unit 14A are continued.

  At time t2, the output unit 14A reads all the image data signal VD3 of frame number f1 from the FIFO buffer 13, completes transfer to the internal bus, and starts processing the image data signal VD3 of next frame number f2. A frame pulse FP is output from the output unit 14A. The frame counter 17 counts up by the frame pulse FP, and the value of the frame number FNO2 becomes f2. Accordingly, the coincidence signal EQU is output from the comparison unit 18, and further, the stop request signal STP is output from the stop control unit 19. Since the stop request signal STP is given to the filter 12 and the output unit 14A, the operation of the entire image data transfer circuit 10A is stopped.

  When the vertical synchronization signal VSYNC of the next frame rises at time t3, the frame counter 15 counts up, the frame number FNO1 becomes f3, and the restart signal RST is output from the frame detector 16. The stop control unit 19 is reset by the restart signal RST, and the output of the stop request signal STP is stopped. As a result, the operation of the entire image data transfer circuit 10A is resumed.

If an output process of the frame f1 is performed by the output unit 14A when an abnormality in the image data is detected at time t1, the frame number FNO2 of the frame counter 17 is f1. Accordingly, the coincidence signal EQU is output from the comparison unit 18, and the stop request signal STP is immediately output from the stop control unit 19. As a result, the operation of the entire image data transfer circuit 10A is immediately stopped.
(Effect of Reference Example 1 )

As described above, the image data transfer circuit of the reference example 1 includes the frame counter 15 that counts the frame number FNO1 that is currently being processed, and the frame counter 17 that counts the frame number FNO2 that is currently being processed. If the two frame numbers FNO1 and FNO2 are different when an abnormality is detected during the input process, the output process is continued, and the stop control unit 19 stops the entire process when these frame numbers FNO1 and FNO2 match. It has. Accordingly, there is an advantage that transfer of only the image data of the frame in which the error has occurred can be stopped without destroying the image data of the normal frame. Further, since the image data transfer circuit is restarted by the start of the next frame after the error has occurred, there is an advantage that the image data of the next frame can be processed normally.

(Configuration of Example 1)
FIG. 1 is a configuration diagram of an image data transfer circuit showing a first embodiment of the present invention . Elements common to those in FIG. 3 are denoted by common reference numerals.
The image data transfer circuit 10B includes an input processing unit 11B, a filter 12B, a FIFO buffer 13B, an output unit 14B, and a frame detection unit 16.

  The input processing unit 11B adds a start bit ST1 for displaying whether or not the image data is the first pixel of a frame to a 24-bit image data signal VD1 that is image data for one pixel, for example, and performs filtering. 12B.

  In addition to the image data signal VD1 and the start bit ST1, the input processing unit 11B outputs an image data valid signal VA1 indicating whether the image data signal is normal and indicating the timing of the image data signal. It is supposed to be.

  The filter 12B is obtained by adding an activation unit 12r to the filter 12a with a reset function. That is, the filter 12a performs predetermined filtering processing according to the image data signal VD1 and the image data valid signal VA1, and outputs the filtered image data signal VD2 in synchronization with the image data valid signal VA2. The filter 12a has a function of returning to the initial state when the restart signal RST is given. On the other hand, the activation unit 12r provides the start bit ST1 as a restart signal RST for the filter 12a, and the start bit ST1 for the FIFO buffer 13B according to the timing of the image data signal VD2 output from the filter 12. This is output as ST2.

The FIFO buffer 13B sequentially stores the image data signal VD2 and the start bit ST2 in accordance with the image data valid signal VA2, and reads them as the image data signal VD3 and the start bit ST3 in the order in which they are stored in response to a read request from the output unit 14B. Is. The output unit 16B is obtained by adding an activation unit 14r to the output unit 12a with a reset function. That is, the output unit 12a reads the image data signal VD3 from the FIFO buffer 13B and outputs the image data signal VD4 to the internal bus. The output unit 14a has a function of returning to the initial state when the restart signal RST is given. On the other hand, the activation unit 14r gives the start bit ST3 read together with the image data signal VD3 from the FIFO buffer 13B as a restart signal RST for the output unit 14a.
(Operation of Example 1)
Figure 5 is a signal waveform diagram showing the operation of FIG.

  In the input processing unit 11B, when the vertical synchronizing signal VSYNC from the video camera or the like rises and the horizontal synchronizing signal HSYNC rises, and then the image data VDATA of the frame f1 is given, the image data signal of the first pixel of the frame f1 Together with VD1, the start bit ST1 is set to “1”, and the image data valid signal VA1 is output. The image data signal VD1 for the second and subsequent pixels is output together with the image data valid signal VA1 with the start bit ST1 set to “0”.

In the filter 12B, if the start bit ST1 is “1”, a reactivation signal RST is given from the activation unit 12r to the filter 12a. After the filter 12a is set to an initial state, an image data valid signal is input from the input processing unit 11B. The image data signal VD1 given together with VA1 is filtered, and the processed image data is output as an image data signal VD2. On the other hand, the starter 12r outputs a start bit ST2 for the FIFO buffer 13B in accordance with the timing of the image data signal VD2 output from the filter 12a.

  In the FIFO buffer 13B, the image data signal VD2 and the start bit ST2 are sequentially stored in accordance with the timing of the image data valid signal VA2. The image data signal VD2 and the start bit ST2 stored in the FIFO buffer 13B are sequentially read as the image data signal VD3 and the start bit ST3 based on a read request from the output unit 14B. Among these, the image data signal VD3 is supplied to the output unit 14a, and the start bit ST3 is supplied to the starting unit 14r. When the start bit ST3 is “1”, the activation unit 14r outputs a restart signal RST to the output unit 14a. As a result, the output unit 14a is set to the initial state at the first pixel of the frame f1, and the image data signal VD3 given from the FIFO buffer 13B is output to the internal bus as the image data signal VD4.

  Here, at time T1 in FIG. 5, when the output unit 14B reads the image data signal VD3 of the frame f1 from the FIFO buffer 13B and outputs it to the internal buffer as the image data signal VD4, the input is input to the input processing unit 11B. Assume that an abnormality has occurred in the image data VDATA of the frame f2 to be performed. When detecting an abnormality in the image data VDATA, the input processing unit 11B stops the input processing operation at that time, and stops the input processing of the image data VDATA subsequent to the frame f2 and the output to the filter 12B. As a result, the image data valid signal VA1 thereafter becomes invalid (level “0”). As a result, the subsequent image data signals are not input to the filter 12B and the FIFO buffer 13B, and these operations stop in order.

On the other hand, the output unit 14B continues to read the image data of the frame f1 stored in the FIFO buffer 13B and transfer it to the internal bus. When the reading of the image data of the frame f1 and the transfer to the internal buffer are completed, the reading of the image data of the next frame f2 and the transfer to the internal buffer are started.
However, when the FIFO buffer 13B becomes empty at time T3, the read operation of the output unit 14B is also stopped.

When the image data VDATA of the next frame f3 is input at time T4, the input processing unit 11B detects the head of the frame f3 and resumes the image data VDATA capturing operation. Then, the start bit ST1 indicating the start of the frame f3 is set to “1” to output the image data signal VD1, and the image data valid signal VA1 indicating that the image data signal VD1 is valid is output. In the subsequent filter 12B, when the image data signal VD1 having the start bit ST1 set to “1” is detected, the starter 12r initializes the filter 12a, and the processing for the next frame f3 is resumed. The image data signal VD2 of the frame f3 output from the filter 12a is stored in the FIFO buffer 13B together with the start bit ST2. Further, the image data of the frame f3 stored in the FIFO buffer 13B is read by the output unit 14B. When the image data signal VD3 with the start bit ST3 set to “1” is detected, the output unit 14a is initialized by the activation unit 14r, and the process for the next frame f3 is resumed.
(Effect of Example 1)

As described above, when the input processing unit 11B detects the start of a frame, the image data transfer circuit according to the first embodiment adds the start bit ST1 indicating the start of the frame to the image data signal VD1 and outputs it to the subsequent stage. At the same time, the filter 12B and the FIFO buffer 13B are configured to transfer the start bit ST to the subsequent stage. As a result, the output unit 14B can be restarted and transfer data to the internal bus when it detects the start bit ST3, and therefore discards the normal frame image data stored in the FIFO buffer 13B. Without being transferred to the internal bus. Further, since the filter 12B and the output unit 14B are restarted with the start bit ST given for each frame and process the image data, there is an advantage that the abnormal data of the previous frame does not affect the processing of the next frame. There is. Further, in the first embodiment , the capacity of the FIFO buffer 13B is increased by the start bit as compared with the reference example 1 , but there is an advantage that the entire circuit configuration can be simplified.
(Modification)
In addition, this invention is not limited to the said reference example and Example, A various deformation | transformation is possible. Examples of this modification include the following.
(A) If the filtering process for the input image data VDATA is not required, the filters 12 and 12B need not be provided.

(B) Although the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC are used as the timing of the image data VDATA, it is sufficient if there is a frame synchronization signal indicating the start timing of the frame.

10A, 10B Image data transfer circuit 11A, 11B Input processing unit
12, 12B filter 13, 13B FIFO buffer 14A, 14B output unit 15, 17 frame counter 16 frame detection unit 18 comparison unit 19 stop control unit

Claims (3)

An image data valid signal indicating whether or not the image data given in accordance with the frame synchronization signal is valid is output in units of pixels, and whether or not the image data is the first pixel of a frame when no abnormality is detected in the image data An input processing unit that adds a start bit for displaying the image data signal and outputs it as an image data signal, and stops outputting the image data signal when an abnormality is detected in the image data ;
A buffer that sequentially stores the image data signal output from the input processing unit in accordance with the image data valid signal, and reads the stored image data signal in the stored order according to a read request ;
The image data signal is read from the buffer and transferred to the outside. When the start bit of the read image data signal indicates the first pixel of the frame, the image data signal is restarted by the start bit. and that the output unit,
An image data transfer circuit comprising: The image data transfer circuit according to claim 1 further processes the image data signal output from the input processing unit based on the image data valid signal output from the input processing unit and stores the processed image data signal in the buffer. With a filter,
The filter is restarted by the start bit when the start bit of the image data signal indicates that it is the first pixel of a frame, and the image data signal is changed according to the image data valid signal. After performing a predetermined filtering process, output in synchronization with the image data valid signal,
The buffer sequentially stores the image data signal output from the filter in accordance with the image data valid signal output from the filter, and reads the stored image data signal in the stored order according to a read request. An image data transfer circuit. The image data transfer circuit according to claim 2, further comprising:
Start that outputs a restart signal that restarts the output unit when the image data signal output from the buffer indicates that the start bit of the image data signal is the first pixel of a frame An image data transfer circuit comprising a unit.

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