JP4387488B2 - Overflow protection circuit and image transmission apparatus using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an overflow protection circuit and an image transmission apparatus using the overflow protection circuit, and more particularly to an overflow protection circuit for preventing overflow of a first-in first-out memory in which data writing and reading are performed asynchronously and an image transmission apparatus using the same.
[0002]
[Prior art]
In general, as shown in FIG. 6, the image transmission apparatus in the video conference system is provided in each of its own station and other stations. In the other-station image transmission apparatus B, image data input from the camera is converted into digital data by the AD converter 51, passes through the preprocessing unit 52, is encoded by the encoding unit 53, and is transmitted to the transmission buffer memory 54. Written in. The written data is sent to the local image transmission apparatus A through the multiplexer (MUX) 55. In the local station image transmission apparatus A, data is written into the reception buffer memory 41 via the demultiplexer (DMUX) 40. Then, the data is decoded by the decoding unit 42, passed through the post-processing unit 43, converted to analog data by the DA conversion unit 44, and output to the monitor.
[0003]
Also in the local-side image transmission apparatus A, image data input from the camera is converted into digital data by the AD converter 35, passes through the preprocessing unit 36, is encoded by the encoding unit 37, and is transmitted. It is written in the memory 38. The written data is sent to the image transmission apparatus B on the other station side via the multiplexer (MUX) 39. In the other-station image transmission apparatus B, data is written into the reception buffer memory 47 via the demultiplexer (DMUX) 46. Then, the data is decoded by the decoding unit 48, passed through the post-processing unit 49, converted to analog data by the DA conversion unit 50, and output to the monitor.
[0004]
In addition to the above-described exchange of video and audio encoded data, control information for controlling the game is exchanged. In the image transmission apparatus B, control information input from a remote controller (remote controller) is input to the remote controller receiver 56, superimposed on the image data by the multiplexer 55, and transmitted to the transmission apparatus A. In the transmission apparatus A, control information is output from the demultiplexer 40 to control the encoding unit 37.
[0005]
On the other hand, in the image transmission apparatus A, the low-speed data is input to the low-speed data control unit 45, and the output is superimposed on the image data by the multiplexer 39 and transmitted to the transmission apparatus B. In the transmission apparatus B, low-speed data is output from the demultiplexer 46 and is output via the low-speed data processing unit 57.
[0006]
Here, the low-speed data control unit 45 is a data port such as a well-known RS232C interface, and the low-speed data is used for a camera control signal for capturing video, data transfer, and the like. That is, a control signal is transmitted from the local station side transmission apparatus A to the other station side transmission apparatus B, and the other station transmission apparatus B is controlled by this control signal.
[0007]
As shown in FIG. 7, the low-speed data control unit 45 writes the S / P conversion unit 1 that converts serial data into parallel data, the data FIFO 3 composed of a dual port memory, and the transfer data c. 6, the CPU 4 that reads the transfer data h and outputs it to the MUX 39 in FIG. 6, and the address decoder 5 that decodes the address output from the CPU 4.
[0008]
In such a configuration, the S / P converter 1 converts the input serial data a into parallel data c. The converted parallel data c is written into the data FIFO 3 by the write enable d and the write address e from the write control circuit 2.
[0009]
The read addresses g, j and k output from the CPU 4 are decoded by the address decoder 5 and the decoded address i is input to the data FIFO 3 together with the read address g. Thereby, the data written in the data FIFO 3 is read as read data h. This read data h is once inputted to the CPU 4 and sent out from an arbitrary output port 40.
[0010]
However, this configuration has a drawback that the value of the write address e is overtaken by the value of the read address g and the data FIFO 3 overflows.
[0011]
By the way, a technique for preventing overflow is described in Japanese Patent Laid-Open No. 9-198258. In this publication, as shown in FIG. 8, the stack upper limit value stored in the stack upper limit value setting register 101 and the address on the address line 104 are monitored by the address matching circuit 102, and the two match. When this happens, the CPU 103 is interrupted. In other words, in this publication, when an overflow is detected, the CPU 103 is interrupted, and the CPU that receives the interrupt saves failure information such as the task name at the time of the failure, and then notifies the upper software of the failure. ing.
[0012]
[Problems to be solved by the invention]
In the above-mentioned publication, when an overflow is detected, an interrupt is issued to the CPU, and the CPU that has received the interrupt notifies the upper software of the occurrence of a failure and waits for an instruction from the upper software. In this case, the CPU stops when an overflow is detected. That is, the conventional circuit described in this publication is a circuit for reliably detecting overflow regardless of the CPU operation after detection, and has a drawback that it is impossible to prevent overflow.
[0013]
The present invention has been made to solve the above-described drawbacks of the prior art, and an object of the present invention is to provide a circuit capable of preventing overflow.
[0014]
An overflow protection circuit according to the present invention is an overflow protection circuit for preventing overflow of a first-in first-out memory in which data writing and reading are performed asynchronously, an S / P conversion unit that converts serial data into parallel data, and a dual A data FIFO composed of port memories;
A write control circuit for outputting to the data FIFO a write address for writing output data from the S / P converter to the data FIFO, a CPU for reading the data written in the data FIFO, and the write address A WP register for storing the write pointer (WP) output from the equivalent write control circuit, and a write interrupt pointer (WIP) indicating the upper limit value of the read address indicating the amount of data read by the CPU in one read process The WIP register to be stored, the SP register for storing a step pointer (SP) indicating the point width indicating the amount of data read by the CPU in one reading process, the WP value and the WIP value are compared, and both points A comparator that outputs a first interrupt signal to the CPU when The CPU includes an alarm counter that outputs a second interrupt signal to the CPU, and the CPU to which the first interrupt signal is input reads the data from the data FIFO and simultaneously stores the WIP value stored in the WIP register. Is updated to the upper limit value of the address to which the amount of data to be read by the CPU in one reading process is added, and when the WP value stored in the WP register matches the updated WIP value, the comparator again Outputs the first interrupt signal to the CPU, and the alarm counter is reset when a new WIP value is set in the WIP register and when the first interrupt signal is generated. Each time the value is incremented by 1, the count of the alarm counter is incremented by 1, and the count is the SP register. Outputting a second interrupt signal to stop the count when the count value matches the value of the stored SP characterized in.
[0015]
Further, according to the overflow protection circuit of the present invention, the CPU to which the second interrupt signal is input reads the data from the data FIFO and simultaneously reads the WIP value stored in the WIP register by the CPU once. The amount of data read out in (1) is updated to the upper limit value of the added address.
[0016]
In short, the present invention can detect not only task stack overflow but also FIFO memory overflow that cannot be controlled by a conventional circuit. When a FIFO memory is used as a data transfer means and the reading control is performed by the CPU, the FIFO memory may overflow depending on the processing status of the CPU. This circuit notifies the CPU of the write / read state of the FIFO memory, and outputs an alarm to the CPU when reading from the FIFO memory is not performed for a certain period. In other words, since the CPU issues an alarm when the process of periodically reading from the data FIFO which is configured by a dual port memory or the like and used as a ring buffer is not in time, overflow can be prevented in advance.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Next, an embodiment of the present invention will be described with reference to the drawings. In the drawings referred to in the following description, the same reference numerals are given to the same parts as in the other drawings.
[0018]
FIG. 1 is a block diagram showing an embodiment of an overflow protection circuit used in an image transmission apparatus according to the present invention. In FIG. 1 , a low-speed data control unit 45 includes an S / P conversion unit 1 that converts serial data into parallel data, a data FIFO 3 composed of a dual port memory, and a write control circuit 2 for writing transfer data c. The CPU 4 that reads the transfer data h and outputs it to the multiplexer 39 in FIG. 6 , the address decoder 5 that decodes the address output from the CPU 4, and the WP register that stores the write pointer (WP) s equivalent to the write address e 7, a WIP register 9 for storing a write interrupt pointer (WIP) t, an SP register 11 for storing a step pointer (SP) u, buffers 6 and 8 for outputting only arbitrary data on the memory map of the CPU 4, The comparator 10 that compares WPf and WIPt, and the comparison result of the comparator 10 is inverted. And inverter 13, and a alarm counter 12 for outputting the interrupt w as a read request and WIP setting request to CPU 4. It is assumed that the WP register 7, the WIP register 9, the SP register 11, and the alarm counter 12 operate in synchronization with the clock l sent from the CPU 4.
[0019]
As shown in FIG. 2, the S / P converter 1 includes a flip-flop (hereinafter abbreviated as FF) 14 that takes in the input serial data a with a clock b synchronized with the serial data a, The serial-parallel conversion device 15 configured by 74LS164 and the like, and the register 16 that outputs the converted parallel data as the write parallel data c in the cycle of the counter 18 are configured.
[0020]
On the other hand, as shown in the figure, the write control circuit 2 receives counters 17 and 18 that generate a write address in synchronization with the clock b, and takes the output of the counter 18 with the clock b and the write address e of the data FIFO 3. And the FF 21 which takes in the most significant bit of the counter 17 with the clock b and outputs the write enable d of the data FIFO 3 and the alarm counter enable x. The carry output of the counter 17 is logically inverted by the inverter 20 and becomes the enable y of the register 16. The output of the counter 18 is output as a write pointer f.
[0021]
As shown in FIG. 3, the alarm counter 12 includes the FFs 22 and 23 that differentiate the comparison result v between WPf and WIPt, the inverter 24 and the NAND gate 25, and the address decoder 5 when the WIPt is set by the CPU 4. The AND gate 26 that outputs a reset signal to the counter 27 and the alarm counter enable x that is output from the write control circuit 2 in FIG. When the FFs 30 and 31, the inverter 32 and the NAND gate 33, the AND gate 34 that outputs the SP set value u and the enable for counting up the counter 27, and the output result of the counter 27 and the SP set value u are equal Outputs an interrupt w that becomes a read request and WIP setting request to the CPU 4 It is configured to include a NAND gate 28 and an inverter 29. It is assumed that the FFs 22, 23, 30 and 31 and the counter 27 operate in synchronization with the clock l sent from the CPU 4.
[0022]
In such a configuration, serial transfer data a input from the RS232C port or the like is input to the FF 14 in FIG. 2 and converted into parallel data by the serial / parallel conversion device 15. Here, when the data width is 16 bits, the inversion of the carry of the counter 17 is enabled and the data is taken in by the FF 16 and converted into the data of the cycle of the counter 18. The counter 18 is composed of the number of stages for outputting the bit width of the address area of the data FIFO 3.
[0023]
Since the data cycle is the cycle of the counter 18, the MSB of the counter 17 can be set to the write enable e, and the write timing is determined by the quantity (number of stages) of the FF 21. The output of the counter 18 is input to the WP register 7. The CPU 4 performs reading in the processing time that can be read by itself.
[0024]
The output of the counter 18 is also input to the comparator 10. The comparator 10 compares WPf, which is the write address of the data FIFO3, with WIPt. As a result of this comparison, when the WP value and the WIP value match, an interrupt v permitting reading is output to the CPU 4. Since the CPU 4 does not read unless the interrupt v is input, the read operation does not overtake the write operation.
[0025]
Furthermore, since the write address s is notified to the CPU 4 by the WP register 7, it is possible to grasp to what extent the data FIFO 3 has been written. When the interrupt v is input, the CPU 4 updates the WIP value. The read control of the data FIFO 3 is performed by updating the WIP.
[0026]
Here, with reference to FIG. 4, the operation of WPf and WIPt on the memory capacity will be described. The capacity of the data FIFO 3 is, for example, 8 Kbytes. As shown in FIG. 4A, the CPU 4 reads WP. Here, the read width is 20 bytes. The CPU 4 sets the value of WIP to WP + 20 and is reset.
[0027]
The write pointer WP is incremented by the data clock, and the comparator 10 compares WPf and WIPt. As shown in FIG. 4B, the WP value matches the WIP value (WP = WIP). ) Generates an interrupt v. This state is shown in FIG. Simultaneously with the occurrence of this interrupt, the CPU is reset.
[0028]
When the interrupt v is input, the CPU 4 updates the previously set WIP value +20 as a new WIP. This state is shown in FIG. The hatched portion in the figure is the CPU read area.
[0029]
Here, when the new WIP is not set instantaneously, the alarm counter 12 operates. This operation will be described with reference to FIG. In the figure, the counter 27 is reset when the comparison result is WP = WIP or when WIP is set. The counter 27 is incremented when the alarm counter enable x in FIG. 1 is input, that is, when data is written to the data FIFO 3, and the write pointer WP is incremented.
[0030]
When the value of SPu becomes equal to the output of the counter 27, the counter 27 stops counting and outputs an interrupt w that becomes a read request and a WIP setting request to the CPU 4.
[0031]
The output operation of the interrupt w will be described with reference to FIG. As shown in FIG. 5A, the CPU 4 performs WIP setting and SP setting. As shown in FIG. 5B, when the value of WP matches the value of WIP, the counter 27 is reset and the data is counted up when data is written to the data FIFO3. The counter 27 is not reset until WIP is set, and counts up to the SP set value (here, “20”).
[0032]
Here, when the WP reaches a value that can be taken by the WIP earlier than the CPU 4 sets the WIP, that is, when the WP exceeds WIP = WIP + 20 as shown in FIG. 5C, Since the output of the counter 27 is “20”, an interrupt w serving as a read request and a WIP setting request is output to the CPU 4. This interrupt w notifies that the data FIFO3 is overflowing. In response to this notification, a read warning (warning) interrupt is generated, and the previously set WIP value +20 is updated as a new WIP. This state is shown in FIG. A portion indicated by slant lines in FIG.
[0033]
When a read warning interrupt is generated, the write pointer WP + α is set as a new WIP. This state is shown in FIG.
[0034]
Returning to FIG. 1, in this circuit, write pointer (WP) f, write interrupt pointer (WIP) t, alarm counter 12 and step pointer (SP) u equivalent to the write address e are prepared in the write control of the data FIFO 3. Has been. Then, when the value of WPf and the value of WIPt match, an interrupt v permitting reading is output to the CPU 4. The value of WIPt is the upper limit value of the read address indicating the amount of data read by the CPU 4 in one read process, and the CPU 4 updates the value. Since the CPU 4 does not start reading until the value of WPf matches the value of WIPt, the write address e cannot be overtaken by the read address g and the read data h cannot be erroneous.
[0035]
WIPt is updated when an interrupt v permitting reading is input to the CPU 4. When the newly set value of WIPt matches the value of WPf, an interrupt v is output to the CPU 4 again.
[0036]
By the way, if the CPU 4 takes time for other data processing and the WPf passes the value to be set next before the setting of WIPt, the data FIFO 3 is composed of a ring buffer, so the write data c is overwritten. It is possible. Therefore, an alarm counter 12 and a step pointer (SP) u are prepared. The SP register 11 stores the width of the amount of data read by the CPU 4 in one reading process.
[0037]
The alarm counter 12 is reset when the WIP register 9 is set and when an interrupt v (interrupt when WP = WIP matches) occurs. When WPf is incremented by 1, the alarm counter 12 is similarly incremented by 1. Similarly, when the value stored in the SP register 11 is counted, the count is stopped , and an interrupt w serving as a read request and a WIP setting request for the CPU 4 is started.
[0038]
In a circuit in which a data FIFO is provided to perform data transfer and the CPU performs read control of the data FIFO, the CPU constantly monitors the write address and generates a read address so as not to overtake the write address. In the circuit according to the present invention, a load is imposed on data processing other than that in which the CPU generates a read address, and an alarm is generated when the periodic read processing is not in time.
[0039]
As an example, in the data FIFO 3 having a capacity of 8 Kbytes, control is performed to start reading when writing of 20 bytes is completed. The address e is output from the write control circuit 2 and the value of WIP is set to “20”. The CPU 4 goes to read WPf at a certain cycle. Here, the value of WP is “20”, and since the value of WP and the value of WIP match, an interrupt is output to CPU 4. Thereafter, if the WIP value cannot be set to “40” before the WPf value becomes “40”, the alarm counter 12 operates.
[0040]
Since the CPU 4 reads every 20 bytes, the value “20” is stored in the SP register 11. The alarm counter 12 is reset when an interrupt occurs when the WP value and the WIP value match, and starts counting up to “20”, which is the value stored in the SP register 11. If WIP is set during the count, the alarm counter is reset, but when “40”, which is the value to be set next as WIPt, is passed, a read request and a WIP setting request are made to the CPU 4 Raise interrupt w. By outputting such a read permission interrupt and a read and WIP setting request interrupt w serving as a protection function to the CPU 4, even if the load on the CPU is heavy, an alarm can be output before overflowing.
[0041]
【The invention's effect】
As described above, according to the present invention, it is possible to prevent memory overflow in an image transmission apparatus using a CPU by providing an interrupt that causes a read alarm when the read is not performed for a certain period of time, such as when the CPU cannot perform normal processing. There is an effect that it can be prevented beforehand.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a low-speed data control unit of an image transmission apparatus according to an embodiment of the present invention.
2 is a block diagram showing an example of the internal configuration of an S / P converter and a write control circuit in FIG.
FIG. 3 is a block diagram showing an example of the internal configuration of an alarm counter in FIG. 1;
FIG. 4 is a diagram illustrating a state in a data FIFO of a low-speed data control unit during normal operation.
FIG. 5 is a diagram showing a state in a data FIFO of a low-speed data control unit during an alarm generation operation.
FIG. 6 is a block diagram illustrating a configuration of a general image transmission apparatus.
FIG. 7 is a diagram illustrating a configuration example of a conventional low-speed data control unit.
FIG. 8 is a block diagram showing a configuration of a prior art that issues an interrupt in response to an overflow.
[Explanation of symbols]
1 S / P converter 2 Write control circuit 3 Data FIFO
4 CPU
5 Address decoder 6, 8 Buffer 7 WP register 9 WIP register 10 Comparator 11 SP register 12 Alarm counter 13 Inverter

Claims (2)

An overflow protection circuit for preventing overflow of a first-in first-out memory in which data writing and reading are performed asynchronously, an S / P converter for converting serial data into parallel data, and a data FIFO comprising a dual port memory A write control circuit for outputting to the data FIFO a write address for writing output data from the S / P converter to the data FIFO, a CPU for reading the data written in the data FIFO, and the write A WP register for storing a write pointer (WP) output from the write control circuit equivalent to an address;
A WIP register that stores a write interrupt pointer (WIP) that indicates an upper limit value of a read address that represents the amount of data that the CPU reads in a single read process, and a point that represents the amount of data that the CPU reads in a single read process and SP register for storing the step pointer (SP) for the width, a comparator for outputting a first interrupt signal to the CPU when both points by comparing the values of the WP and WIP matches, the CPU Consists of an alarm counter that outputs a second interrupt signal ,
The CPU, to which the first interrupt signal is input, adds the amount of data that the CPU reads the WIP value stored in the WIP register at the same time as reading the data from the data FIFO. The upper limit value of the address is updated, and when the WP value stored in the WP register matches the updated WIP value, the comparator outputs the first interrupt signal to the CPU again .
The alarm counter is reset when a new WIP value is set in the WIP register and when the first interrupt signal is generated. Each time the WP value is incremented by 1, the alarm counter is incremented by 1. An overflow protection circuit which is incremented and stops counting and outputs a second interrupt signal when the count matches the value of SP stored in the SP register . The CPU to which the second interrupt signal is input reads the data from the data FIFO and simultaneously adds an amount of data for the CPU to read the WIP value stored in the WIP register in one reading process. The overflow protection circuit according to claim 1, wherein the overflow protection circuit is updated to an upper limit value .

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