JP3856016B2 - Signal processing device - Google Patents

Description

  The present invention relates to a signal processing apparatus that processes recording / reproduction / transmission / reception of a digital signal, and particularly relates to processing of an abnormal state or a data error.

The processing operation in the digital signal processing apparatus is usually designed in consideration of an abnormal state such as an error occurrence. For example, in consideration of the occurrence of an abnormal situation, it is considered that the system operates correctly as long as it is reset periodically as appropriate, and correct data is input even if the signal processing apparatus enters an abnormal state. Patent Document 1 discloses a technique for resetting a circuit when a predetermined code pattern in data is detected as an example of such a technique.
Japanese Patent Application Laid-Open No. 7-143489

  However, when a predetermined code pattern used for reset periodically is inserted in the input data, if the predetermined code pattern is detected using the method described in Patent Document 1, the reset is performed. Even correct data in a storage circuit such as a register in the apparatus is erased, which causes a serious problem in that signal processing cannot be performed correctly.

  In view of the above problems, the present invention can perform reset even when a predetermined code pattern used for reset periodically is inserted in the input data, and even if the signal processing device falls into an abnormal state, The purpose is to provide a mechanism that operates correctly when correct data is input.

  Further, in the conventional signal processing device, in the signal processing device that controls the input signal using the input permission signal, when the input permission signal becomes inactive, the data is also held in the internal circuit. .

  However, in a device in which data is input even after the input permission signal becomes inactive, there is a big problem that data after the input permission signal becomes inactive is lost.

  The present invention has been made in view of the above problems, and even in an apparatus in which data is input even after the input permission signal becomes inactive, the data after the input permission signal becomes inactive is not lost without being lost. The present invention provides a signal processing apparatus that can process well.

  In order to achieve the first object, the signal processing apparatus according to the present invention is reset when the internal processing is completed and the pattern is periodically input or the internal processing is not completed. When a pattern to be performed is input, a reset standby is performed, and the reset is performed after the internal processing is completed.

  In order to achieve another object, the signal processing device according to the present invention holds the data after the input permission signal becomes inactive in the storage device and does not output it until the input permission signal becomes active. It is characterized by that.

  According to the signal processing device of the present invention, it is possible to perform reset even when a predetermined code pattern used for reset periodically is inserted in the input data, and it is correct even if the device falls into an abnormal state. Works correctly if data is entered.

  Further, even when data is input after the input permission signal becomes inactive, the data after the input permission signal becomes inactive can be processed successfully without being lost.

  In the signal processing device according to the first aspect of the present invention, even when a predetermined code pattern used for reset periodically is inserted in the input data, the reset can be performed, and even if the device falls into an abnormal state If correct data is input, it has a mechanism to operate correctly.

The signal processing device according to the first aspect of the present invention receives at most c symbols after the input permission signal becomes inactive, processes the input signal for b symbols at a time, and outputs the processed signal . signal processing means for notifying its own internal overflow condition if the signal processing capability overflow state of said signal processing means, and the input enable signal generating means for outputting the input permission signal inactive, the input signal When the input permission signal is active, b symbols are output to the signal processing means, and the relationship between a, b, and c is always a ≧ (b + c), and the input permission is retained. it is characterized in that it comprises a register using the calculated signal the logical sum of the first latch signal and said input enable signal the signal as a load signal.

In the signal processing device according to the first aspect of the present invention, the data after the input permission signal becomes inactive can be processed without being lost.

  Here, the symbol represents a processing unit such as a byte or a word.

In the signal processing device according to the second aspect of the present invention, after the input permission signal becomes inactive, a signal of at most c symbols is input, the input signal is processed and output, and the input signal processing means for outputting a signal for notifying whether it is possible to accept the signal, a memory for output to the signal processing means stores the input signal, when the signal processing means which can accept the signal, the Write / read control means for controlling the memory so as to read data from the memory and outputting the write address and the read address while performing write control so as not to overwrite unread data, and the write / read control means when said write allowance represented by difference of the write address and said read address becomes at least c symbol It is characterized in that it comprises a an input permission signal generating means for outputting the input permission signal inactive.

In the signal processing device according to the second aspect of the present invention, the data after the input permission signal becomes inactive can be processed successfully without loss of data.

  Embodiments of a signal processing apparatus according to the present invention will be described below in detail with reference to the drawings.

(Embodiment 1)
First, the signal processing apparatus according to Embodiment 1 of the present invention will be described. As a specific example, a DVD device is assumed. FIG. 1 is a block diagram showing the configuration of a signal processing apparatus according to the present invention. In FIG. 1, 1 is a head pattern detector, 2 is a reset generation and input permission signal generation circuit, 3 is a signal processing circuit, 5 is a first register, 6 is a second register, 7 is a third register, 8 Is the fourth register.

  The operation of the embodiment of the present invention will be described with reference to FIG.

  In order to easily understand the first embodiment, the data format of the input signal is 8-byte parallel input of 1 byte, 2048 bytes is a unit, and the head pattern is 32 bits (4 bytes) 000001BA (hexadecimal) Assume that This conforms to the DVD recording standard and the format of DVD equipment such as DVD video and DVD audio player.

  One byte of data is sequentially input in units of 2048 bytes. Input data is sequentially held in the first register 5, the second register 6, the third register 7, and the fourth register 8. Then, in the unit of 4 bytes, the first register 5, the second register 6, the third register 7, and the fourth register 8 are simultaneously input to the signal processing circuit 3 and processed and output. The signal processing circuit 3 not only processes and outputs a signal from each register, but also indicates whether the circuit itself is operating or not, that is, whether the signal is being processed or has been processed. To the reset generation and input permission signal generation circuit 2. The head pattern detector 1 monitors the data in the first register 5, the second register 6, the third register 7, and the fourth register 8 to detect 000001BA (hexadecimal number) which is the head pattern. For example, the reset generation and input permission signal generation circuit 2 is notified that the head pattern has been detected. The reset generation and input permission signal generation circuit 2 receives the notification of the start pattern detection from the start pattern detector 1 in a state where the signal processing circuit 3 has received the notification that the signal processing has been completed. Output a reset signal. On the other hand, when the reset generation and input permission signal generation circuit 2 receives a notice of head pattern detection in a state where the signal processing circuit 3 has not completed the signal processing, the input permission signal is deactivated and the input signal is stopped. Internally holds a signal indicating that it is ready to reset. Holding a signal indicating that it is ready to perform this reset is called reset standby. When the signal processing circuit 3 notifies the processing completion in the reset standby state, the reset generation and input permission signal generation circuit 2 outputs the reset signal to the signal processing circuit 3 and cancels the reset standby state. The reset generation and input permission signal generation circuit 2 deactivates the input permission signal and stops the input signal when the signal processing circuit 3 overflows.

  Although one unit is 2048 bytes, it may be any value such as 1024 bytes, 188 bytes, 194 bytes. Furthermore, although the head pattern is 32 bits of 000001BA (hexadecimal), for example, 32 bits of 000001BB, 00000100 (hexadecimal), 28 bits of 000001e (hexadecimal), 8 bits of 47 (hexadecimal), etc. Good value. Further, the signal processing circuit 3 may be divided and configured by a plurality of signal processing devices.

  As described above, it is possible to periodically perform resetting, and even when the apparatus falls into an abnormal state, it is possible to provide a mechanism for operating correctly if correct data is input.

(Embodiment 2)
Next, a signal processing apparatus according to Embodiment 2 of the present invention will be described with reference to FIGS. FIG. 2 is a block diagram of the signal processing apparatus according to the second embodiment. FIG. 6 is a timing chart in the circuit from the input signal, the input permission signal, and the registers 5 to 10. FIG. 6 shows the case where the input permission signal is negated. In FIG. 2, 4 is a signal processing circuit, 5 is a first register, 6 is a second register, 7 is a third register, 8 is a fourth register, 9 is a fifth register, and 10 is a sixth register. A register, 11 is an input permission signal generation circuit, 21 is a logical sum, and 22 is a 1 latch register. The differences between the second embodiment and the first embodiment will be described below. The first embodiment can be reset periodically, and has the purpose of providing a mechanism for operating correctly if correct data is input even if the apparatus falls into an abnormal state. Form 2 is intended to successfully process the data after the input permission signal becomes inactive without losing data when the data is input after the input permission signal becomes inactive. .

  The operation of Embodiment 2 of the present invention will be described with reference to FIG.

  In order to easily understand the second embodiment, it is assumed that the signal processing device is input in units of one byte of 8-bit parallel, and one byte is input after the input permission signal is inactive. Input data is sequentially held in the first register 5, the second register 6, the third register 7, the fourth register 8, the fifth register 9, and the sixth register 10. Then, 4 bytes of data in the third register 7, the fourth register 8, the fifth register 9, and the sixth register 10 are simultaneously input to the signal processing circuit 4, processed, and output. The signal processing circuit 4 not only processes the input data and outputs the data, but also notifies the input permission signal generation circuit 11 as the overflow notification signal of the state immediately before the overflow occurs. Although a specific situation of occurrence of overflow is not a feature of the present invention, an example is given. In the signal processing circuit 4, the input signal is held in a register for calculation. The processing speed is constant. On the other hand, when the input speed of the input signal is variable, the input speed may temporarily exceed the processing speed of the signal processing circuit 4. In such a case, the register of the signal processing circuit 4 may overflow. When the overflow notification signal is input to the input permission signal generation circuit 11, the input permission signal generation circuit 11 outputs the deactivated input permission signal. The subsequent data flow will be described with reference to the timing chart of FIG. The input data input to the signal processing apparatus of the second embodiment is stopped by the inactive input permission signal, but 1-byte data is input to the first register 5 (input signal D8 in FIG. 6). . The registers from register 5 to register 10 are controlled by a load signal. The result obtained by logically ORing the signal obtained by latching the input permission signal (register 22 output in FIG. 2) and the input permission signal (logical output 21 in FIG. 2) is used as a load signal.

  The signal processing circuit 4 detects an overflow at timing A in FIG. Then, after one clock, that is, at timing B, the input permission signal is deactivated (negated). At this time, the input signal D7 is input and must be taken into the first register 5. The first register 5 is controlled by a load signal. At timing A, the load signal is active. Therefore, the input signal D7 is successfully taken into the first register 5. Further, when the input permission signal becomes inactive (negated) at timing B, 1 byte (D8) is input as an input signal. At this time, since the load signal is active, the signal (D8) can be successfully captured. At timing C, the input signal is also stopped. The overflow of the signal processing circuit 4 is released, and the input signal is restored at timing D, which is the timing when the input permission signal becomes active (D9). In FIG. 6 showing the flow of this signal, even if the input permission signal is inactive (negated), the output signals of the third register 7 to the sixth register 10 input to the signal processing circuit 4 are continuous. It can be seen that there is no missing input data.

  Although it is assumed that data is input in bytes with 8-bit parallel as 1 byte and that 1-byte data is input to the signal processing device after the input permission signal is inactive, the input unit, input permission The amount of input data after the signal is inactive may be arbitrary.

  As described above, in the signal processing device of this embodiment, when data is input after the input permission signal becomes inactive, data after the input permission signal becomes inactive is dropped. It can be processed successfully without any problems.

(Embodiment 3)
Next, a signal processing apparatus according to Embodiment 3 of the present invention will be described with reference to FIG. In FIG. 3, 1 is a head pattern detector, 5 is a first register, 6 is a second register, 7 is a third register, 8 is a fourth register, 9 is a fifth register, and 10 is a sixth register. , 12 is a write / read control circuit, 13 is a register, 17 is a signal processing circuit, 18 is a reset generation and input permission signal generation circuit, 21 is a logical sum, and 22 is a 1 latch register. The third embodiment is different from the first and second embodiments in that the signal processing circuits 3 and 4 shown in FIGS. 1 and 2 are divided into a write / read control circuit 12, a register 13, and a signal processing circuit 17. It is the point which becomes composition. Therefore, in the second embodiment, the data from the third register 7 to the sixth register 10 is output when the input permission signal is active. However, in the third embodiment, the input permission signal is active. Is used as a condition for permitting writing by the write / read control circuit 12 and the mechanism of the first embodiment is combined.

  The operation of the third embodiment will be described with reference to FIG.

  In order to easily understand the operation of the third embodiment, the input signal is assumed to be 1 byte of 8-bit parallel, 2048 bytes as one unit, and the head pattern is 32 bits (4 bytes) of 000001BA (hexadecimal). Assume that one byte is input after the input permission signal becomes inactive. The assumption that 2048 bytes are a unit and the leading pattern is 32 bits (4 bytes) of 000001BA (hexadecimal number) is in accordance with the DVD recording standard, the DVD video standard, and the DVD audio standard.

  One byte of data is sequentially input in units of 2048 bytes. Input data is sequentially held in the first register 5, the second register 6, the third register 7, the fourth register 8, the fifth register 9, and the sixth register 10. Then, the outputs of the four registers from the third register 7 to the sixth register 10 are written into the register 13. The write / read control circuit 12 controls the register 13. If there is a writable area in the register 13, the write / read control circuit 12 permits writing and starts writing data. If there is unread data in the register 13, the write / read control circuit 12 reads the unread data from the register 13 and outputs it to the signal processing circuit 17. Further, if the write / read control circuit 12 tries to write data to the unread data area in the register 13, the write is prohibited, and at the same time, the write prohibition is written to the reset generation and input permission signal generation circuit 18. Notify by prohibition notification signal. Further, the write / read control circuit 12 notifies the reset generation and input permission signal generation circuit 18 of the unread data remaining notification signal as to whether or not there is unread data in the register 13. The output from the register 13 is input to the signal processing circuit 17. The signal processing circuit 17 processes and outputs the input signal, and instructs the write / read control circuit 12 to stop reading with a read stop signal when an overflow occurs. Further, if the data being processed does not remain inside the signal processing circuit 17, the signal processing circuit 17 is a processing completion signal to the reset generation and input permission signal generation circuit 18, and the data being processed does not remain. Notify that. When the reset generation and input permission signal generation circuit 18 receives a write prohibition notification, the reset generation and input permission signal generation circuit 18 immediately deactivates the input permission signal and stops the input signal. Since the operations from the register 5 to the register 10 after the input permission signal becomes inactive are the same as those in the second embodiment of the present invention, they are omitted here.

  On the other hand, the head pattern detector 1 monitors the first register 5, the second register 6, the third register 7, and the fourth register 8 to detect 000001BA (hexadecimal number) which is a head pattern of one unit. Then, the reset generation and input permission signal generation circuit 18 is notified that one unit of head pattern has been detected. In the reset generation and input permission signal generation circuit 18, the signal processing circuit 17 is in the process of receiving a notification from the write / read control circuit 12 that data that has not been read into the register 13 does not exist in the register 13. If a notification that the head pattern has been detected is received from the head pattern detector 1 in a state where the notification that the data is not present exists, a reset signal is sent to the write / read control circuit 12 and the signal processing circuit 17. Output. Also, when receiving a notification from the head pattern detector 1 that the head pattern has been detected, it is notified from the write / read control circuit 12 that data that has not been read exists in the register 13, or signal processing is performed. If at least one of the notifications that the data is being processed is received from the circuit 17, a reset standby is made, the input permission signal is deactivated, and the input is stopped. Here, the meaning and operation of reset standby are the same as in the first embodiment. If the notification that the data that has not been read from the write / read control circuit 12 does not exist in the register 13 and the notification of the completion of processing from the signal processing circuit 17 are received, the reset generation and input permission signal generation circuit 18 receives the write / read control circuit 12. The reset signal is output to the signal processing circuit 17 to cancel the reset standby state. At the same time, the input permission signal is activated.

  Needless to say, the head pattern of one unit may be other than the head pattern shown in the third embodiment as in the first embodiment. Further, one unit may be other than 2048 bytes. Furthermore, there may be an input of 1 byte or more after the input permission signal becomes inactive. However, in this case, it is necessary to increase the number of input register stages.

  As described above, according to the signal processing device according to the present embodiment, it is possible to perform resetting periodically, and even if the device falls into an abnormal state, it has a mechanism that operates correctly if correct data is input. In the case where data is input after the input permission signal becomes inactive, a mechanism that can be processed successfully without losing data after the input permission signal becomes inactive It has the effect of being combined.

(Embodiment 4)
Next, a signal processing device according to Embodiment 4 of the present invention will be described with reference to FIG. In FIG. 4, 14 is an input permission signal generation circuit, 15 is a write / read control circuit, 16 is a memory, and 19 is a signal processing circuit. The fourth embodiment of the present invention differs from the third embodiment in that the processing of data after the input permission signal becomes inactive is not a register but a FIFO (First In First Out) type memory or a similar address. This is a point that is performed by a memory that performs control.

  In order to easily understand the fourth embodiment, it is assumed that 4 bytes are input in units of 4 bytes (32 bits parallel), and 4 bytes are input after the input permission signal is inactive.

  Signals are sequentially input to the memory 16. The memory 16 is controlled by the write / read control circuit 15. The write / read control circuit 15 permits writing if an input signal is present. If there is readable data in the memory 16 and the signal processing circuit 19 can accept it, the writing / reading control circuit 15 starts reading and outputs it from the memory 16 to the signal processing circuit 19. Further, the write / read control circuit 15 notifies the input permission signal generation circuit 14 of the read address and the write address. When the difference between the read address and the write address is 2, the input permission signal generation circuit 14 deactivates the input permission signal and stops the input signal. After the input enable signal becomes inactive, 4 bytes are input. Since this is one address of the memory 16, the read address and the write address indicate the same value even if written to the memory 16. There is no. That is, data that has not yet been read is not overwritten. When the read address advances and the difference between the read address and the write address exceeds 2, the input permission signal becomes active. Thereby, the 4 bytes after the input permission signal becomes inactive are not lost. The signal processing circuit 19 processes the input data and outputs it. Further, the signal processing circuit 19 instructs the write / read control circuit 15 to stop reading immediately before the overflow occurs.

  Needless to say, the unit size of the input data may be a parameter other than the assumption as in the other embodiments.

  As described above, when data is input after the input permission signal becomes inactive, the data after the input permission signal becomes inactive can be processed successfully without being lost.

(Embodiment 5)
Next, a signal processing device according to Embodiment 5 of the present invention will be described with reference to FIG. In FIG. 5, 1 is a head pattern detector, 5 is a first register, 6 is a second register, 7 is a third register, 8 is a fourth register, 18 is a reset generation and input permission signal generation circuit, 15 is a write / read control circuit, 16 is a memory, and 20 is a signal processing circuit. The fifth embodiment of the present invention is different from the fourth embodiment in that the fourth embodiment and the third embodiment are combined.

  In order to easily understand the fifth embodiment, it is assumed that the input signal is 1 byte of 8-bit parallel, 2048 bytes are a unit, and the head pattern is 32 bits (4 bytes) of 000001BA (hexadecimal), Assume that 1 byte is input after the input permission signal becomes inactive. Further assume that memory 16 is a 32-bit data bus.

Signals are sequentially input to the first register 5, the second register 6, the third register 7, and the fourth register 8. Here, since the operation of the head pattern detector 1 is the same as that of the first embodiment, it is omitted here. Then, data from the first register 5 to the fourth register 8 is simultaneously written in the memory 16. Write / read control of the memory 16 is performed by the write / read control circuit 15. Since the operation of the write / read control circuit 15 is the same as that of the third embodiment, it is omitted here. Data read from the memory is input to the signal processing circuit 20. Since the signal processing circuit 20 is the same as that of the fourth embodiment, it is omitted here. Since the operation of the reset generation and input permission signal generation circuit 18 is the same as that of the fourth embodiment, it is omitted here. Since the reset operation is the same as that of the third embodiment, it is omitted here. Hereinafter, since the operation when the input permission signal becomes inactive is different, this point will be described.

  Assume that a signal is input to the memory 16, the difference between the read address and the write address is 2, and the input permission signal becomes inactive. At this time, since 1 byte of input data is input, data exists in the first register 5. Furthermore, after the input permission signal becomes inactive, there is a 1-byte input, so that data exists in the first register 5 and the second register 6. Soon, if the difference between the read address and the write address is 3 or more, the input permission signal becomes active and a signal is input.

  As described above, it can be reset periodically, and even if the device falls into an abnormal state, if correct data is input, it will not only have a mechanism to operate correctly but also after the input permission signal becomes inactive. In the case where data is input, a mechanism that can be processed successfully without missing data after the input permission signal becomes inactive is organically coupled. In the case of this embodiment, there is an additional 1 byte. That is, after the input permission signal becomes inactive, the input signal can be accepted up to 2 bytes.

  The signal processing apparatus of the present invention is useful for processing when an abnormal state or a data error occurs in a signal processing apparatus that processes recording / reproduction / transmission / reception of a digital signal.

Signal processing block diagram of the signal processing apparatus according to Embodiment 1 of the present invention Signal processing block diagram of the signal processing apparatus according to the second embodiment of the present invention Signal processing block diagram of a signal processing apparatus according to Embodiment 3 of the present invention Signal processing block diagram of a signal processing apparatus according to Embodiment 4 of the present invention Signal processing block diagram of a signal processing apparatus according to Embodiment 4 of the present invention Input side timing chart of signal processing apparatus according to Embodiment 2 of the present invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Leading pattern detector 2 Reset generation | occurrence | production and input permission signal generation circuit 3 Signal processing circuit 4 Signal processing circuit 5 1st register 6 2nd register 7 3rd register 8 4th register 9 5th register 10 6th Register 11 input permission signal generation circuit 12 write / read control circuit 13 register 14 input permission signal generation circuit 15 write / read control circuit 16 memory 17 signal processing circuit 18 reset generation and input permission signal generation circuit 19 signal processing circuit 20 signal processing circuit 21 OR 22 1 latch register

Claims (4)

After the input permission signal becomes inactive, a signal for at most c symbols is input,
With an input signal b symbol processing and outputs at a time, and signal processing means for notifying its own internal overflow condition,
If the signal processing capability overflow state of said signal processing means, and the input enable signal generating means for outputting the input permission signal inactive,
Said input signal retaining a symbol, the input enable signal to output the b symbol in the case of the active to the signal processing means, the relationship of the a and the b and the c are located at always a ≧ (b + c) A register that uses, as a load signal, a signal obtained by calculating a logical sum of a signal obtained by latching the input permission signal and the input permission signal ;
A signal processing apparatus comprising: 2. The signal processing apparatus according to claim 1, wherein a symbol is 6 bytes, b symbol is 4 bytes, and c symbol is 2 bytes. After the input permission signal becomes inactive, a signal for at most c symbols is input,
Outputs by performing processing on the input signal, a signal processing means for outputting a signal for notifying whether it is possible to receive the input signal,
A memory for storing the input signal and outputting it to the signal processing means;
When the signal processing means can accept a signal, the memory is controlled to read data from the memory, and the write address and the read address are set while performing write control so as not to overwrite unread data. Write / read control means for outputting;
When the write margin amount indicated by the difference between the write address and the read address from the write read control means becomes at least c symbol, the input enable signal generating means for outputting the input permission signal inactive ,
A signal processing apparatus comprising: Either the c symbol is 3 bytes or less, the data access width of the memory is 32 bits, and the difference between the read address and the write address of the memory is 2 or the signal processing means cannot accept the input signal. 4. The signal processing apparatus according to claim 3, further comprising an input permission signal generating means for outputting the input permission signal in an inactive state when one of the conditions is established.

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