JP4103452B2 - Data input control device for serial EEPROM - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data input control device for controlling input of serial data in a serial EEPROM in which input serial data is stored in a nonvolatile memory cell.
[0002]
[Problems to be solved by the invention]
The serial EEPROM serially inputs and outputs data stored in a nonvolatile memory cell for the purpose of minimizing the number of signal lines. Some data input control is configured to use a chip select signal in order to reduce control signal lines.
[0003]
FIG. 4 shows an example of a timing chart of data input and writing in such a type serial EEPROM. That is, when the level of the high active chip select signal CS changes from low to high, a start bit, a write command, an address, and data are serially input to the data input terminal DI in synchronization with the serial clock SK. At this time, the input data is serial / parallel converted in the shift register.
[0004]
Then, when the level of the chip select signal CS changes from high to low, the process of writing the data held in the shift register to the EEPROM memory cell is started.
[0005]
However, in the serial EEPROM having such a configuration, since data input control is performed by referring to the level of the chip select signal CS, for example, when noise is applied to the chip select signal, the data input is in progress. However, there is a problem that when the level of the chip select signal changes to low, input data may be written at that time.
[0006]
The present invention has been made in view of the above circumstances, and its purpose is to write incomplete data into a memory cell when noise is applied to the chip select signal during the input cycle. It is an object of the present invention to provide a data input control device of a serial EEPROM that can be surely prevented.
[0007]
[Means for Solving the Problems]
According to the serial EEPROM data input control device of the first aspect, when one edge of the chip select signal input to the serial EEPROM is detected, the serial data input is permitted based on the detected edge and the data input is performed. If the other edge is detected before the end of the cycle, input of serial data is prohibited based on the edge detection.
[0008]
That is, for example, when writing the serial data by changing the chip select signal output from the microcomputer to the serial EEPROM, the chip select signal changes from inactive to active, and changes from active to inactive. Depending on the case, different edges of the chip select signal are detected. If one edge means the start of the data input cycle, the other edge means the end of the input cycle.
[0009]
Since data is input to the serial EEPROM according to a predetermined format, it is possible to determine which stage the input is in by referring to the input state of the data. Therefore, if the other edge of the chip select signal is detected before the data input cycle is completed, the change timing of the signal is clearly abnormal. It is possible to reliably prevent complete data from being written into the memory cell.
[0010]
The first flip-flop, along with becoming detects one edge of the chip select signal to a set state to allow the input of the serial clock, the shift for in synchronization with the serial clock for serial / parallel conversion of the input data Release the reset of the register. Accordingly, serial data can be input to the shift register by detecting one edge.
[0011]
When the second flip-flop detects the other edge of the chip select signal before the end of the data input cycle, the second flip-flop enters a set state and outputs a signal for resetting the first flip-flop. Then, at that time, the input of the serial clock is prohibited and the shift register is reset, so that the input of serial data is prohibited. Therefore, the data input control device can be configured with a simple configuration.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described below with reference to FIGS. FIG. 2 shows an electrical connection between a microcomputer 1 and a serial EEPROM (hereinafter simply referred to as EEPROM) 2. The microcomputer 1 includes a CPU, a ROM, a RAM, and the like inside. It also includes a parallel / serial conversion circuit, a serial / parallel conversion circuit, an address decoder, etc., which are interfaces for writing and reading data to / from the EEPROM 2 (none of which are shown).
[0013]
When the microcomputer 1 writes data to the EEPROM 2, the chip select signal CS is made active (high level) and the serial clock signal SK is output to the serial clock terminal of the EEPROM 2, and at the data input terminal DI, Write commands, write addresses, and write data are serially output.
[0014]
Similarly, when the microcomputer 1 reads data, the chip select signal CS is similarly activated to output the serial clock signal SK, and a read command and a read address are sequentially serially output to the data input terminal DI. The read data output serially from the data output terminal DO is received. The reset signal is output at the time of power-on reset by a reset circuit (not shown).
[0015]
FIG. 1 shows the inside of the EEPROM 2 mainly with a data input control unit (data input control device) 3 according to the gist of the present invention as a center. In the following, in order to avoid complication, the same name is used for the terminal of the EEPROM 2 and its signal name. The input data DI is given to one input terminal of the AND gate 4, and the chip select signal CS is given to the other input terminal. The output terminal of the AND gate 4 is connected to the data input terminal D of the reception register unit 5. It is assumed that data output from the output terminal of the AND gate 4 is “di”.
[0016]
The serial clock signal SK output from the microcomputer 1 is supplied to the clock input terminal CLK of the D flip-flop 6 (FF 3) and also to the clock input terminal CLK of the reception register unit 5 through the AND gate 7. ing. The data input terminal D of the D flip-flop 6 is pulled up, and its output terminal Q is connected to another input terminal of the AND gate 7. Note that the clock signal output from the output terminal of the AND gate 7 is “sk”.
[0017]
The reception register unit 5 includes a shift register that performs serial / parallel conversion on input serial data in synchronization with a clock signal sk. The instruction input to the reception register unit 5 is output to the command decoder 8 and decoded. The address and data input to the reception register unit 5 are distributed and stored in an address buffer and a data buffer (not shown). A control logic unit (not shown) performs processing such as data writing, reading, and erasing with the memory cell 9 based on the decoded instruction.
[0018]
Further, the chip select signal CS is given to the clock input terminal CLK of the D flip-flop (first flip-flop, FF1) 10 and also through the NOT gate 11 to the D flip-flop (second flip-flop, FF2) 12. The clock input terminal CLK is also provided.
[0019]
The output terminal Q of the D flip-flop 10 is given to each reset terminal RST (low active) of the reception register unit 5 and the D flip-flops 6 and 12, and the output terminal Q of the D flip-flop 12 is connected to the AND gate 13. It is connected to one input terminal. The data input terminals D of the D flip-flops 10 and 12 are both pulled up.
[0020]
The reception completion signal output unit 14, the command end signal output unit 15, and the clock excess signal output unit 16 generate and output timing signals used in the control inside the data input control unit 3.
[0021]
When the signal level supplied from the output terminal Q of the D flip-flop 10 becomes high, the reception completion signal output unit 14 counts the number of input bits of the data di based on the clock signal sk. When the number of data bits corresponding to the instruction content decoded by the command decoder 8 is counted, a high level reception completion signal is output to the other input terminal of the AND gate 13 via the NOT gate 17. Yes.
[0022]
The reception completion signal is reset when the output signal of the D flip-flop 10 becomes low level. The output signal of the AND gate 13 is given to one input terminal of the 3-input NOR gate 18.
[0023]
When the signal level applied from the output terminal Q of the D flip-flop 12 becomes high, the instruction end signal output unit 15 counts the clock signal WR_ck used for the process of writing the input write data into the memory cell 9. When the number of write clocks corresponding to the instruction content decoded by the command decoder 8 is counted, a high-level instruction end signal is output to another input terminal of the NOR gate 18 in a monopulse.
[0024]
When the signal level applied from the output terminal Q of the D flip-flop 10 becomes high, the clock excess signal output unit 16 counts the number of input clocks of the clock signal sk. Then, when the number of input clocks of the clock signal sk determined according to the content of the instruction decoded by the command decoder 8 is exceeded, a high level clock excess signal is output to the other one input terminal of the NOR gate 18. It has become.
[0025]
The output signal of the NOR gate 18 is output to one input terminal of the negative logic OR gate 20 via the delay element 19. The other input terminal of the OR gate 20 is supplied with a row active reset signal, and the output terminal of the OR gate 20 is connected to the reset terminal of the D flip-flop 10.
[0026]
Although the illustration of the configuration on the data output side that operates when reading data from the EEPROM 2 is omitted, a part of the reception register unit 5 is also used when outputting data.
[0027]
Next, the operation of this embodiment will be described with reference to FIG. FIG. 3 is a timing chart when the microcomputer 1 writes data into the EEPROM 2. The microcomputer 1 sets the chip select signal CS to high level (see (a), time point (1)) and outputs the serial clock signal SK (see (c)).
[0028]
Then, since the output terminal Q of the D flip-flop 10 in the data input control unit 3 detects the rising edge of the chip select signal CS and becomes high level (see (i) or (j)), the reception register unit 5 and The reset of the D flip-flop 6 is released. Since the D flip-flop 6 is continuously set by the rising edge of the serial clock signal SK, the AND gate 7 can output the clock signal sk (see (h)).
[0029]
The AND gate 4 can also output the data di when the chip select signal CS becomes high level (see (g)), and the reception completion signal output unit 14 and the clock excess signal output unit 16 perform the respective counting operations. Start.
[0030]
Then, when the microcomputer 1 outputs an instruction (in this case, writing) to the first two bits as input data DI (see (b), time point (2)), it subsequently outputs the writing address and writing data serially. (Refer to point (3)).
[0031]
When the input cycle for writing is normally performed, the reception completion signal output unit 14 outputs a reception completion signal at time point (4) when the last data is input (see (d)). Then, after outputting all the serial data, the microcomputer 1 sets the chip select signal CS to the low level (see time point (5)). At this time, the output terminal Q of the D flip-flop 12 detects the falling edge of the chip select signal CS and becomes high level, but since the reception completion signal is output, the AND gate 13 does not become high level.
[0032]
When the reception completion signal is output, a write process for writing the write data set in the data buffer of the reception register unit 5 into the memory cell 9 is started. Then, a write clock signal WR_ck is output by a write processing unit (not shown), and the instruction end signal output unit 15 counts the number of output clocks. When a predetermined number of write clocks is counted, the instruction end signal output unit 15 outputs an instruction end signal (see time point (6)).
[0033]
Since the instruction end signal is output to the OR gate 20 via the NOR gate 18 and the delay element 19, the D flip-flop 10 is reset at the timing when the delay time is given by the delay element 19 (time point 7). ▼). Accordingly, the reception register unit 5 and the D flip-flops 6 and 12 are also reset accordingly.
[0034]
Here, it is assumed that noise is applied to the chip select signal CS that is at the high level at the time point (8) while the input cycle is being performed. Then, the output terminal Q of the D flip-flop 12 detects its fall and becomes high level.
[0035]
At this time, since the reception completion signal output unit 14 does not output the reception completion signal, the AND gate 13 becomes high level and the D flip-flop 10 is reset (see (i), time point 9). Accordingly, the input cycle is stopped at this point, and incomplete data is prevented from being written in the memory cell 9 in the middle of the cycle.
[0036]
After that, the microcomputer 1 can determine that the writing has failed if the verification process is performed to check whether the data is actually written correctly by reading the data to be written to the predetermined address of the EEPROM 2. In this case, the same data may be rewritten to the same address.
[0037]
The clock excess signal output unit 16 counts the number of input clock signals sk from the start of the input cycle. For example, noise is applied to the serial clock signal SK in the same manner as the above-described chip select signal CS. Then, when the number of input clocks exceeds a predetermined value before the instruction completion signal is output, a clock excess signal is output (see (f), time point (10)). At that time, the D flip-flop 10 is reset and the input cycle is stopped.
[0038]
As described above, according to the present embodiment, when the data input control unit 3 detects the rising edge of the chip select signal CS input to the EEPROM 2 by the microcomputer 1, the data input control unit 3 permits the input of the serial data DI based on the edge detection. At the same time, if a falling edge is detected before the end of the data input cycle, the input of serial data DI is prohibited based on the detected edge.
[0039]
Specifically, when the D flip-flop 10 detects the rising edge of the chip select signal CS, the D flip-flop 10 is set, permits the input of the serial clock signal SK, cancels the reset of the reception register unit 5, and the D flip-flop 12. However, when the falling edge of the chip select signal CS is detected before the reception end signal is output, the D flip-flop 10 is reset in the set state.
[0040]
That is, if the falling edge of the chip select signal CS is detected before the end of the data input cycle, the change timing of the signal is clearly abnormal. Thus, it is possible to reliably prevent incomplete data from being written into the memory cell 9.
[0041]
The present invention is not limited to the embodiments described above and shown in the drawings, and the following modifications or expansions are possible.
The delay element 19 is unnecessary when a sufficient hold time for resetting the D flip-flop 10 can be secured by the gate delay time of the NOR gate 18 or the OR gate 20.
The chip select signal CS may be low active. In this case, the falling edge of the signal may be detected by the first flip-flop, and the rising edge may be detected by the second flip-flop.
The clock excess signal output unit 16 may be provided as necessary.
[Brief description of the drawings]
FIG. 1 is a diagram showing an internal configuration of a serial EEPROM according to an embodiment of the present invention, mainly showing a data input control unit according to the gist of the present invention. FIG. 2 is an electrical connection state between a microcomputer and a serial EEPROM. FIG. 3 is a timing chart when the microcomputer writes data to the serial EEPROM. FIG. 4 is an example of a timing chart of data input and writing in the conventional serial EEPROM.
2 is a serial EEPROM, 3 is a data input controller (data input controller), 5 is a reception register (shift register), 9 is a memory cell, 10 is a D flip-flop (first flip-flop), and 12 is a D flip-flop. (Second flip-flop) is shown.

Claims (1)

Serial EEPROM is configured such that serial data is input while the chip select signal is active, and then the input data is written to the memory cell when the chip select signal changes to inactive. In the data input control device for controlling the input of the data,
When one edge of the chip select signal input to the serial EEPROM is detected, serial data input is permitted based on the edge detection, and when the other edge is detected before the data input cycle is completed, the edge detection is performed. intended to prohibit the input of the serial data based,
When one edge of the chip select signal is detected, the set state is set, so that the input of the serial clock is permitted and the shift register for performing the serial / parallel conversion of the input data in synchronization with the serial clock is reset. A first flip-flop to be released;
And a second flip-flop that outputs a signal that resets the first flip-flop when the other edge of the chip select signal is detected before the data input cycle is completed. A data input control device for serial EEPROM.

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