JPS60181851A - Partial writing control system - Google Patents

Abstract

PURPOSE:To simplify the partial writing process at both start and finish time points of block transfer by performing the partial writing for an area between the bype position shown by a memory address and the final byte of a word with the 1st memory access for block transfer and then for an area between the 0-th byte of the word and the byte position showing the memory address with the final memory access respectively. CONSTITUTION:In the 1st memory access of block transfer, the data (a, A-C) of 4 bytes selected by a selector circuit 34 are delivered to a memory array 10 via a register 32 to perform the partial writing for an area between the byte position shown by a memory address (memory start address 4n+1). The final memory access of block transfer is decided when the coincidence is obtained between the contents of an address counter 52 and the bits excluding lower 2 bits of a memory and address stored in an address register 53. Thus the data (X-Z, z) of 4 bytes selected and delivered from the circuit 34 are delivered to the array 10 via the register 32. Then the partial writing is performed for an area between the 0-th byte of the corresponding word and the byte position shown by a memory address (memory end address 4n'+2).

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to block transfer from an input/output device to a memory, and particularly relates to a partial write control method at the start and end of block transfer.

[Technical Background of the Invention] Conventionally, half-word write and byte write functions have been applied to this type of partial writing. For example, in the case of block transfer of data A to Z as shown in Figure 1 (memory code address is 4n+1, memory end address is 4
In the case of n=+2), memory access is performed for data from data D to data W in units of 4 bytes (full words). On the other hand, for data A, B, and C at the start of block transfer, A byte write, B,
It was necessary to divide C into half word dry 1 and control it. Similarly, at the end of block transfer, it was necessary to perform halfword writes 1 to 1 for data X and Y, and byte write for data Z.

[Problems with the Background Art] As described above, in conventional partial write control, there are two types of lii! write: pie mill write and half word write. Since the I control is required, the control becomes complicated, and there is also a drawback that partial writing must be performed twice.

[Purpose of the Invention] This invention was made in view of the above circumstances, and its purpose is to provide a partial write control system that can simplify partial write processing at the start and end of block transfer.

[Summary of the Invention] In the present invention, the lower 2 bits 1 to 1 of the memory address of block transfer memory sk-1 are set in accordance with the memory address load signal, and the remaining bits of the memory start address are set to the memory address mentioned above. The address counter is set in response to the load signal and incremented in response to the memory access end signal. A binary 2-bit l to counter that increments i, a first flip 70 that detects the first memory access of a block transfer by sending it to the cell 1 in response to the memory address load signal, and a selector that selects the output data from the above-mentioned register or the output data from the binary 2-bit counter according to the state of the flip-flop; a second register that holds the memory end address of the block transfer; and a second register that holds the memory end address of the block transfer; A comparator that compares the remaining bits of the memory end address excluding the lower two bits with the contents of the address counter and detects a match, and is set according to the comparison result of this comparator and is the last memory access of a block transfer. A channel device equipped with a second flip-flop for detecting this, and memory controllers 1 to 1 for controlling memory access to the memory are provided.

This memory controller 1-0-receives block transfer from the channel device in accordance with each state of the first and second flip-flops and the memory address indicated by the concatenation information of each output data from the address counter and selector. Write data to memory. This memory controller 1
If the first flip-flop indicates that this is the first memory access of a block transfer, the ~ roller writes a portion of the memory address indicated by 1 from the position to the last byte l of the word. Do this. Similarly, if the second flip 70 indicates that this is the last memory access of the block transfer, the memory controller partially accesses the memory from the O-th byte of the word to the byte position indicated by the memory address. Write.

[Embodiment of the Invention] FIG. 2 shows the configuration of main parts of an information processing apparatus according to an embodiment of the invention. In the figure, 10 is a memory array in which one word is 4 bytes, 20 is a memory data bus, and 30 is a memory controller for controlling memory access to the memory array 10. Memory controller 30 is connected to memory array 10 via memory data bus 20. 40 is a DMA bus, and 50 is a channel device. The channel device 5° is connected to an input/output device (not shown) and is also connected to the memory controller 30 via a DMA bus 40.

In the channel device 50, 51 is a memory card address register (SMAR) that holds the lower two bits of the block transfer memory card address in response to a memory address load signal @81, and 52 is a memory access end signal. The address counter (MAR) increments according to 82. The remaining bits of the memory start address are initialized in the address counter 52 in response to the address load signal 81. 53 is a memory end address register (EMAR) that holds the memory end address of block transfer (actually memory end address "-1"), and 54 is a comparator (COMP).

The comparator 54 compares the remaining bits of the memory end address held in the end address register 53 excluding the lower two bits 1 to 1 with the contents of the address counter 52 . 5
5 is a 4-byte counter (48C) that increments according to the data input signal 83 indicating 1-byte data input.
It is. The 4-byte counter 55 has the above memory risk -1.
~The lower two bits of the address are initialized in response to the address load signal @81.

The 4-byte counter 55 is a binary 2-bit counter.

56 is an inverter (INV) to which the access end signal 82 is supplied, and 57.58 is a flip-flop (F/F).
). Preset terminal of flip-flop 57 (P
An address load signal 81 is supplied to the terminal R), and an access end signal 82 is supplied to the clock terminal (CK). Also, the data input terminal (D>
is set to 110 I+ level. On the other hand, the data input terminal (D) of the flip-flop 58 is set to the "1" level.

Further, the output signal from the comparator 54 is supplied to the clock terminal (CK) of the flip-flop 58, and the clear terminal (CK) is supplied with the output signal from the comparator 54.
CLR) is supplied with an output signal from the inverter 5G. 59 is a selector that selects either the address register 51 or the output data (2 bits) from the 4-byte counter 55 according to the Q output signal of the flip-flop 57; 6o is used to supply each Q output signal of the flip-flops 57 and 58; This is an OR gate (OR). selector 5
The 2-bit selection output data from address counter 52 is connected to the lower part of the 30-bit output data from address counter 52, and is used as a memory address for memory array 10.
It is supplied to the memory controller 30 via the A bus 40. The output of 60 to or game 1 is function pin 1-F.
The Q output signal of the flip-flop 58 is used as the function bit 1-'4.

F2. Memory controller 1~ via DMA bus 40 along with F3
○-ra 30 is supplied. In addition, bits FO, F2, F
Since the generation of 3 is not directly related to this invention, its explanation will be omitted. 61 is a 4-by-1 data register (Ilo-DR,) that latches data from the input/output device (Ilo) one byte at a time.

The input position of data from the input/output device to this register 61 is indicated by the contents of 4-by-1 to counter 55.

In the memory controller 30, 31 is a 4-by 1- data register (MRDR) that holds data read from the memory array 10, and 32 is a 4-by 1- data register (MRDR) that holds data written to the memory array 10.
MWDR). 33 is a 4-byte data register (DW) that holds write data from the DMA bus 40.
DR), 34 is a selector circuit consisting of selectors 34-0 to 34-3. Selector 34-+ (i-〇~3)
selects and outputs one of the output data from the bits l-r i J of the registers 31 and 33 in accordance with the selection control signal 5EL1. The output data from the selector 34-1 is supplied to the byte l-r i J position of the register 32.

35 is an address register (DMAR) that holds the memory address from the DMA bus 40; 36 is the DMA bus 40;
A function register (FR) 37 holds the function pins FO to F4, and 37 is a decoding circuit. The decoding circuit 37 decodes the lower two contents of the register 35.
It decodes the contents of the pin 1-1 and the register 36, outputs selection control signals 5ELO to 5EL3, and outputs various memory control signals.

:Next, the operation of one embodiment of this invention will be explained. When a block of data from an input/output device is transferred to the memory array 10, the address load signal 81 becomes active in the IIO11 in the digital device 50, and the lower two bits 1 to 1 of the memory card address are transferred to the address register (SMAR) 5.
1 and 4 by 1 counter (48G) 55 are set. Similarly, memory risk-1~remaining address bit 1~ are set in the address counter (MAR) 52, and the memory end address is set in the address register (EMA, R) 53.
is set to At this time, the flip-flop (F, 'F
) 57 is set in response to the address load signal 81, thereby indicating that this is the first memory access of block transfer. When the flip-flop 57 is active, the selector 59 selects the memory address (lower two bits) from the address register 51.

Data from the input/output device is loaded into the byte position of register (Ilo-DR) 61 indicated by 4-byte counter 55. This 4-byte counter 55 is incremented every 1 byte in response to the data input signal 83. The memory controller 30 has a 4-byte counter 55
The bass refrain is output to the D-1A bus 40 at the timing when the content of ``11'' changes to ``00''.

However, when permission to use the bus is granted from the bypass capacitors 1 to rollers (not shown), the output node j data from the register 61,
Memory address from address counter 52 (upper 30
memory address (lower 2 bits) from selector 59, and function bit F
4 is output to the DMA bus 40. Here, if we consider the case of block transfer of data A to Z as shown in FIG.
The initial setting content is '01'. In this case, the first data A is loaded into the register 61 at the position of file l-[1J, and then the data 81 is loaded into the byte r of the register 61.
Loaded into positions 2J and r3J in order. Then, due to the data input signal 83 accompanying the loading of data C,
The 4-byte counter 55 is incremented, and its contents transition from "'ii" to PAOD II. Therefore, the data output from the channel device @50 to the DMA/@ bus 40 in the first memory access becomes [*ABCJ. When the data output from the channel device 50 to the DMA bus 40 is completed, the access end signal 82 becomes "'1" active/roaring.
is increased by +1, and the flip 70 knob 57 is reset; -.

The data rHABcJ output from the channel device 50 to the DMA bus 40 is held in the register (DWDR) 33 in the memory controller 1-row 530, and the memory address (32 pins) is held in the register (DMAR) 35. and function bits FO to F4 are stored in the register (FL
J) held at 36. The decoding circuit 37 transfers the function hit FO- held in the register 36 to the lower two bits 1 of the memory address held in the register 35.
Decode F4. For block transfers from I/O devices to memory, especially pit t-F1. F2 has meaning.

In this case, F.O.

F3 is 'O'' and F2 is 1''. This indicates the F2I access mode k, and as in this example, a value of "1" indicates a memory write access, and a value of "0'' indicates a memory read access. Note that the explanation of FO and F3 will be omitted because they are not directly related to this invention.

In the first memory access of block transfer, FO-F
4 is 01100'' and indicates block transfer start special access mode. In this case, decoding circuit 3
7 outputs memory control signals and selection control signals 5ELO-8EL3 for read-modify-write 1-. Signals 5ELO to 5EL3t differ depending on the lower two bits of the memory address. The lower 2 bits are '0'
In this example, which is the block transfer first special access mode, 5ELO is "'O", 5EL1~5
EL3tma111! It becomes 1.

Read/modify/write (First, write the remaining bits (30 bits) excluding the lower 2 bits of the address of memo 1.
One word (4 bytes) is read from that area of memory array 10 specified by . This read data is held in the register 31. Read data from the memory array 10 held in the register 31 and channel device 50 (input/output device) held in the register 33
Backing with the data from is performed by the selector circuit 34 (selectors 34-0 to 34-3 within). In this example, data a from the register 31 is selected for byte "0" in response to logic II OI+ signal 5ELO, and data a from register 31 is selected for byte "1" to byte "3".
1 Register 3 according to I+ signals 5EL1 to 5EL3
Data A-C from 3 is selected. In this way, the 4-by-1- data (a.

A, B, C) are connected to the memory array 10 via the register 32.
and written to the area. That is, in the case of the first memory access of block transfer, partial writing is performed from the byte position indicated by the memory address (memory start address 4n+1) to the final byte of the word. This is the operation in block transfer start special access mode.

In the second and subsequent memory accesses of block transfer, the flip 70 knob 57 is reset (unless the flip-flop 58 is set), so the function bit F1 is 0''.In other words, in the second and subsequent memory accesses ( (except for the final memory access), bit F
O to F4 are "00100", and the normal memory write mode is designated. In this mode, channel device 5
o, each time 4 bytes of data (for example, data D, E, F, G for the second time, data H, 1, J for the third time,
A bus request is issued every time the byte counter 55 changes from "11" to "00".

Furthermore, since the flip-flop 57 has been reset, the selector 59 selects the output data from the 4-byte counter 55. Therefore, when the flip 70 knob 57 is reset (normal memory write mode, and furthermore in the block transfer end special access mode described later), the memory is output from the channel device @ 5o to the memory controller 3o via the DMA bus 40. The lower two bits of the address are 'o o'.

In the memory controller 3o, in the normal memory write mode, full word dry 1 to write the 4-byte data from the channel device 5o as is into the memory array 10 is performed.

It is assumed that the transfer from the input/output device to the memory array 10 progresses and the contents of the address counter 52 match the remaining bit 1-, excluding the lower two bits, of the memory end address held in the address register 53.

In this case, the comparator 54 outputs a coincidence detection signal.

Flip-flop 58 is set in response to the match detection signal from comparator 54. This indicates that this is the last memory access of the block transfer.

When the flip-flop 58 is set, the function pitch hF1. F4 becomes 1''. Therefore bit F
O~[4 becomes '01101', and the block transfer end special access mode is designated.

On the other hand, data from the input/output device is loaded into the bye I position of register 61 indicated by 4by1 to counter 55. The 4-by-1 counter 55 is incremented every byte in response to the data input signal 83.

In this way, byte position "O" of register 61.

[11, r'l) l L-;-tax, Y, ;'y+
The memory address indicated by the output data from the address counter 52 and the selected output data from the selector 59 (the output data from the 4-by-1 counter 55) is held in the address register 53. It will match the memory end address of C. this
1.

A match is detected by a comparator (not shown), and unlike before, a bus request is output as a result of this match detection. Therefore, in the last memory access of the block transfer, the data transferred from the channel device 50 to the memory controller 1-0-30 via the DMA bus 40 is rXYZl.

In the memory controller 30, data rXYZl from the channel device 50 is held in the register 33. In addition, the output data from the address counter 52 (in the channel @ 50) and the selected output data from the five selectors (
The memory address (in this example, the memory end address) indicated by the output data from the 4-byte counter 55 is held in the register 35, and the memory address (in this example, the memory end address) indicated by
("01101°.

) is held in the if register 36. In this case, the decoding circuit 37 outputs memory control signals and selection control signals 5ELO to SEL for read/modify/write.
Outputs 3. The signal 5ELO"5EL3 differs depending on the mode and the lower two pips of the memory address.

In this example, 5ELO to 5EL2 are PA1°', 5EL3
"o" roars. Lead King Defy Lie 1~
First, the memory array 10 specified by the remaining bits (30 bits 1~) excluding the lower two bits 1 of the memory address.
One word (4 by 1~) is read from that area.

This read data is held in the register 31. In this way, the backing of the read data from the memory array 10 held in the register 31 and the data from the channel device 50 (input/output device) held in the register 33 is performed by the selector circuit 34 (selectors 34-0 to 34-0 in the register 34). 34-3)
This is done by In this example, for fl-rOJ ~ byte "2", the signal SEL of logic II 1 II
○~5 Data X~Z from register 33 according to EL2
is selected, and error 1g3” Q
Data Z from the register 31 is selected in response to the signal 5EL3 of "4 by 1- data (X, Y.

7, z) is output to the memory array 10 via the register 32 and written into the area. That is, in the case of the last memory access of a block transfer, the memory address (memory end address 4 n
Partial writing to pi1-[f indicated by '+2) is performed. This is the operation in block transfer final special access mode.

[Effects of the Invention] As detailed above, according to the present invention, partial write processing at the start and end of block transfer can be simplified, and moreover, memory access processing at the start and end of block transfer can be performed only once. , it is also possible to speed up block transfer.

[Brief explanation of the drawing]

FIG. M1 is a diagram for explaining conventional block transfer, FIG. 2 is a block configuration diagram of an information processing device according to an embodiment of the present invention, and FIG. 3 is a diagram for explaining block transfer in the configuration of FIG. 2. . DESCRIPTION OF SYMBOLS 10...Memory array, 30...Memory controller, 34...Selector circuit, 37...Decode circuit, 50 Channel device for 51...Memory start address register (SMAR), 52...Address Counter (MAR>53...Memory end address register (EMAR) 54...-Comparator 54.55...4
Buy 1~Counter (4BC) 57, 58...Flip-flop (F/F), 59.34-0~34-3
···selector. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] Lower 2 bits 1 of memory start address for block transfer
~ is set in response to the memory address load signal, the remaining bits of the memory start address are set in response to the memory address load signal, and increment I~ is set in response to the memory access end signal.
An address counter in which the lower two bits of the memory start address are set in response to the memory address load signal, and a binary 2-bit 1-counter that increments by 1 for each byte, in response to the memory address load signal. A first flip-flop that detects the first memory access of a block transfer, and selects the output data from the first register or the binary 2-bit counter according to the state of the first flip-flop. a selector that holds the memory end address for block transfer, a comparison that compares the remaining bits of the memory end address held in this second register, excluding the lower two bits, with the contents of the address counter and detects a match. a second flip-flop that is set according to the comparison result of the comparator to detect that it is the last memory access of a block transfer; and each state of the first and 27th flip-flops; and a memory controller that writes the data to be block transferred from the channel device to the memory according to the memory address indicated by the concatenation information of each output data from the address counter and the selector, and the first memory access of the block transfer. In this case, a partial write is performed from the pie 1 position indicated by the above memory address to the last byte of the word, and if it is the last memory access of a block transfer, the data is written from the 0th byte of the word to the last byte of the word. A partial write control method that performs partial writing every time up to the indicated byte position.