JPH0455962A - Memory card - Google Patents

Abstract

PURPOSE:To protect data by securing an exclusive OR between each bit of the data written in a memory element and each bit of the data (identification number) shifted by a shift register and outputting these data to a data bus. CONSTITUTION:An exclusive OR is secured between each bit of the data read out of a memory element 1 with the address and the read signal received from a CPU and each output (Q0, Q1,..., Q15) of a shift register 2 by the exclusive OR circuits 4a0, 4a1,..., 4a>=15 respectively. Then each bit of the OR data is outputted through each of 3-state buffer circuits 4b0, 4b1,...,4b15 and then sent to a data bus of a CPU via the terminals DB0, DB>=1,..., DB15 respectively. At the same time, the read-out data are decided correct when the data stored temporarily in the register 2, i.e., an identification number is equal to the one set when the data are written into the element 1. As a result, the data is protected.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a memory card used as an external storage device for personal computers, etc., and more specifically, it relates to a memory card used as an external storage device for personal computers, etc., and more specifically, it relates to a memory card that is used as an external storage device for personal computers, etc. This is about memory cards that can be used.

[Conventional Example] In recent years, advances in LSI technology have led to the development of large-capacity memory elements, and IC cards have been proposed to replace magnetic cards. There are memory cards with built-in .

Since memory cards are small and easy to store, they are used as external storage devices in, for example, personal computers, and are expected to become even more popular in the future.

[Problem to be solved by the invention] By the way, memory cards can be used by anyone.
Since anyone can read the data on the memory card, confidentiality may be an issue. That is, there is a problem in that data that should not be known to others cannot be written to the memory card.

The present invention was made in view of the above-mentioned problems, and its purpose is to provide a memory card with a read protection function that allows only a specific user to read data.

[Means for Solving the Problems] In order to achieve the above object, the present invention connects to an address bus, a data bus, etc. of a CPU, writes data to a memory element via the data bus, and writes data to a memory element via the data bus. A memory card that can read and output data includes a shift register that shifts and stores serial data (PIN number) from the CPU, and a shift register that shifts and stores serial data (PIN number) from the CPU, each bit of the data shifted to this shift register, and the data that is transmitted via the data bus. a first logic circuit group for taking an exclusive OR with each bit and writing the ORed data into the memory element; each bit of the data written in the memory element and the shift register; and a second logic circuit group for performing an exclusive OR with each bit of the data (PIN number) shifted into the data bus and outputting the ORed data to the data bus. This is the summary.

[Function] With the above configuration, when writing data to a memory card, if a PIN number is entered in a device in which the memory card is loaded, such as a personal computer, the data of this PIN number will be transferred to the memory card. Shifted and stored in a shift register. Thereafter, when a data write operation is performed, this data and the bits of the data stored in the shift register are exclusive-ORed, and this exclusive-ORed data is written to the memory element.

On the other hand, when reading data from the memory card, if a PIN number is entered in a device loaded with the memory card, such as a personal computer, the data of this PIN number is shifted and stored in the shift register of the memory card. . After this, when a data read operation is performed, the data from the memory element and the bits of the data stored in the shift register are exclusive ORed, and
This exclusive ORed data is output to the data bus of the CPU of the personal computer. In this case, if the PIN entered is the same as when writing the data, the read data is correct, but if the PIN is different, the read data is incorrect. .

In this way, the data on the memory card can only be used by the person who wrote it, and will not be used by other people.

[Embodiment] Hereinafter, an embodiment of the present invention will be described based on FIGS. 1 to 4.

In FIG. 1, the memory card has a memory element (for example, R
AM; static RAM) 1, a shift register 2 for shifting and storing a personal identification number (serial data) unique to the user of this memory card, and a shift register 2 for shifting and storing a personal identification number (serial data) unique to the user of this memory card; each bit of and each output of the shift register 2 (Q, , Q,
, . . . , take the exclusive OR of each bit of that data and each output of the shift register 2 (Q, , Q, , ..., Q□5), and send the ORed data to the address bus. A second logic circuit group 4 that enables output is provided.

Further, when the write or read data is 16 bits, the first logic circuit group 3 outputs each bit of the write data and the output of the shift register 2 (Q, , Q
, ..., Q-engine), 16 two-person exclusive OR circuits (Ex-OR circuits) 3aa,
A three-state buffer circuit 3b0゜3b1... which outputs the outputs of 3a, +"' t3 als, and each exclusive OR circuit (Ex-OR circuit) 3aov3axp..., 3a engineering to the memory element 1. , 3b□, and the second logic circuit group 4 similarly receives each bit of the read data and the output of the shift register 2 (Q,
16
Two-person exclusive OR circuit (Ex-OR circuit) J
an 44 ax v ”' y 4 axs and each exclusive OR circuit (Ex-OR circuit) 4a, 4a□, -
,4a□.

Three-state buffer circuits 4 b, , 4 bl, . . . , 4 b output the outputs of 4 to the data bus of the CPU.
It consists of engineering, and. In this case, the three-state buffer circuits 3 b, , 3 b□, . . .
3b engineerings, 4b, -4b□.

..., 4b1. is in a high impedance state (floating state) at "H" level, an inverter circuit 5 is provided to invert the read signal (■ signal) from the CPU, and this inverter circuit 5 inverts the read signal (RD The doubled signal is input to the gate terminals of the three-state buffer circuits 3b, , 3b, .・・・
・It is designed to be input to the gate terminal of 4b□.

And three-state buffer circuit 3b0゜3b□
,..., 3b□, are connected to the data lines (Do, D, , D, ,...-Dts) of the memory element 1, and the three-state buffer circuits 4b, , 4b,...
・The output of 4b0 is the data bus (DB, , DBl, D
B, ,...=DBzs).

Note that when a memory card is loaded into a personal computer, etc., the data bus (DB, , DB) of the CPU is
terminals connected to address buses and control lines (SO, SC, RD, VR) are provided. The SD terminal is for inputting serial data from the CPU and shifting this data to shift register 2, and the SC terminal is for inputting the clock from the CPU and enabling shift operation of shift register 2. belongs to. Also, as in the past, the read signal (■ signal) via the RD terminal is input to the read terminal of the memory element 1, and the write signal (■ signal) via the VR terminal is input to the read terminal of the memory element 1.
The WR multiplied signal is input to the write terminal of the memory element 1, and the address signal via the address bus terminal is input to the address terminal of the memory element 1.

Next, the operation of the memory card with the above configuration will be explained in Figures 2 to 4.
The explanation will be based on the time chart shown in the figure.

First, to write data to the memory card.

After loading the memory card into, for example, a personal computer, the user inputs a personal identification number unique to the user in the personal computer before writing or reading data thereon. Then, the personal identification number data (for example, 16 bits) is output in serial format from the CPU of the personal computer. At this time, Fig. 2 (a
) and (b), a clock is output together with the serial data, this serial data is input to the memory card through the SD terminal, and a clock is input to the memory card through the SC terminal. is,
Since the serial data is shifted into the shift register 2, the data of the above-mentioned password is temporarily stored.

Subsequently, when the user performs a data write operation, the write data is output to the data bus of the CPU.

The write data is input to the memory card through the terminal (as shown in FIG. 3(b)). At this time, the CP
From U, the address of the write data is output to the address bus of the CPU (shown in Figure 3 (a)), and a write signal (WR times signal) and a read signal (Hyakumo signal) are output to the control line. (Figure 3(e) and (d)
), these addresses, write signals, and read signals are input to the memory card through each terminal.

Since the read signal (RD double signal is at "H" level in the CPU write cycle (shown in FIG. 3(d)), each three-state buffer circuit 3 bo, 3 of the first logic circuit group 3 b□, . . . , 3b, are in an output enabled state, and the three-state buffer circuits 4bo, 4b, . . . , 4b in the second logic circuit group 4 are in a floating state.

Subsequently, the data inputted through the terminals DBo, DBl, . Exclusive OR with each bit of is taken. Each bit of this ORed data is
State buffer circuits 3 b, , 3 bl,...
, 3b1. The signal is output to the memory element 3 via (shown in FIG. 3(c)). At this time, as described above, since the address of the write data is input to the memory element 1 through each terminal, and the write signal (WR multiplied signal is input through the WR terminal), the above exclusive The ORed data will be written into the memory element 3.

Similarly, when a data write operation is performed by the user of the memory card, each bit of the data and each output of the shift register 2 (Q, , Q, ) are written.

. . , Q, .

On the other hand, when reading data from the memory card, first load the memory card into a personal computer or the like and input the password. in this case.

The password is the one used when writing data to the memory card. Then, the CPU of that personal computer sends the data of that PIN number (for example, 16
Since the bits) are output in serial format, the data of the password is shifted to the shift register 2 and stored in the same manner as described above.

Subsequently, when the user performs a data read operation, the CPU outputs the address of the write data to the CPU address bus (shown in FIG. 4(a)), and also outputs the read signal (R 5 signal) and write signal (WR times signal) are output to the control line (Fig. 4 (
d) and (e)).

These addresses, read signals, and write signals are input to the memory card via each terminal.

Since the read signal (RD) is at the "L" level at the data write timing (as shown in FIG. 4(d)), each three-state buffer circuit 3b0, 3b□ of the first logic circuit group 3, ..., 3b are in a floating state, and each three-state buffer circuit 4b, , 4bl, ..., 4b of the second logic circuit group 4
i becomes ready for output.

Subsequently, each bit of the data read from the memory element 1 and each output of the shift register 2 (Q,, Q□, . . . ,
Q engineering S) is each exclusive OR circuit 4a0゜4a□,...
・Exclusive OR is performed at t”all. Each bit of this ORed data is output from each three-state buffer circuit 4b, , 4b□,..., 4b, and further The data is DB, , DBl,...
The data temporarily stored in the shift register 2, that is, the password, is output to the data bus of the CPU via the terminal DBl (as shown in FIG. 4(b)). If it is the same as when it is written, the data read out to the data bus of the CPU of a personal computer or the like will be correct data (original data at the time of writing). However, if the data shifted and stored in the shift register 2, that is, the PIN number, is different, then the C
The data read to the data bus of the PU is not correct data.

Note that the shift register 2 is cleared, for example, when the memory card is loaded into a personal computer or when it is pulled out.

In this way, the memory card is provided with a shift register 2 for shifting and storing the data of the user's unique PIN number, and when writing or reading data, the user's unique PIN number is written in the shift register 2, The write data or read data and the shifted data are exclusive-ORed, and this logical data is used as the write data of the memory element 3 and also as the read data of the memory card, so when reading data from the memory card, the write If you do not enter a number that matches the PIN number at the time of writing, it will be impossible to read the correct data, and only those who know the PIN number at the time of writing will be able to use the data on the memory card. , the confidentiality of the data can be maintained.

In addition, in the above embodiment, a case was explained in which only one PIN number was shifted into the shift register 2, but if the person using the memory card manages the PIN number,
For example, even if you change the password while writing data to the same memory card, the correct data can be read out.

[Effects of the Invention] As explained above, the memory card of the present invention has a shift register that shifts and stores serial data (PIN number) from the C, PU of a personal computer or the like in which the memory card is loaded. , take the exclusive OR of each bit of the data temporarily stored in this shift register and each bit of the data via the data bus of the CPU,
and a first logic circuit group for writing the ORed data into the memory element, each bit of the data written in the memory element, and each bit of the data (PIN code) shifted to the shift register. Take the exclusive OR with the bit, and send this ORed data to the CPU.
A second logic circuit group is provided for inputting 8 inputs to the data bus of the memory card, so when you want to use the data on the memory card, you have to enter the PIN used when writing the data and input that PIN to the shift register. If the number data is not shifted, the correct data cannot be read out, and the memory card is not used by others, so the data can be protected.

[Brief explanation of the drawing]

FIG. 1 is a schematic partial block diagram of a memory card showing an embodiment of the present invention, FIG. 2 is a time chart explaining the operation of the memory card, and FIG. Write Cycle Diagram FIG. 4 is a read cycle diagram when reading data to the memory card. In the figure, 1 is a memory element (RAM), 2 is a shift register, 3 is a first logic circuit group, 3ao, 3a, ・
・・3 a□,, 4all, 4a,, -, 4Bi, are exclusive OR circuits (2EX-OR), 3b,, 3b,, -
,3b,,,4bI,,4b1? ...4bi is a three-state buffer circuit, 4 is a second logic circuit group, 5
is an inverter circuit. Figure 1 Patent Applicant: Fujitsu General Corporation Agent, Patent Attorney Takuya Ohara Figure 2 Figure 3 Figure 4

Claims (2)

[Claims] (1) In a memory card that is connected to the address bus, data bus, etc. of a CPU, and is capable of writing data to a memory element via the data bus and reading data from the memory element, the serial data (password A shift register for shifting and storing a number), and exclusive ORing of each bit of the data shifted to the shift register and each bit of data via the data bus, and calculating the ORed data. a first logic circuit group for writing to the memory element; and exclusive OR of each bit of data written to the memory element and each bit of data (PIN number) shifted to the shift register. and a second logic circuit group for outputting the ORed data to the data bus. (2) The first and second logic circuit groups include a number of exclusive OR circuits (Ex-OR circuits) corresponding to the number of bits of the data.
2. The memory card according to claim 1, each comprising a three-state buffer circuit and a three-state buffer circuit.