JPS5914316A - Protecting controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in a protection control device that protects and controls an electric power system using a digital arithmetic device such as a microcomputer.

[Technical background of the invention]

When protecting and controlling a power system using a digital processing device such as a microcomputer, for example, in a protective relay device, it is conventional to set each setting value of the protective relay element in a protective disconnection device. A method is often adopted in which the data is stored in two memory circuits and used to perform predetermined protection calculations. That is, when changing the set value, the new drug set value after the change is written in the first memory circuit,
The old setting value before the change is stored in the second storage circuit.

After the change of the set value is completed, the new drug constant value stored in the first memory circuit is transferred to the second memory circuit,
Both the contents of the first and second memory circuits are set as new drug constant values.

Normally, writing and transferring of these new drug values is performed by operating a switch or the like. Here, providing two memory circuits is a waste of reliability; for example, constant protection calculations are performed using the old setting values stored in the second memory circuit, and Checking whether the written new setting value is within a predetermined setting range (hereinafter referred to as absolute value check), or checking whether it has a predetermined magnitude relationship with the setting value of other elements (
(hereinafter referred to as relative value check). In case of incorrect setting, if the setting value is set to an external alarm, etc., even if an incorrect setting value is written to the first memory circuit, as long as it is not transferred to the second memory circuit, The protection calculation will be performed using the old specified value. Further, after transferring the new setting value to the second storage circuit, it is also possible to check whether the setting values of the two storage circuits are equal.

[Problems with background technology]

By the way, in a conventional protection control device equipped with such a setting device, when an incorrect setting is performed as described above, the above-mentioned absolute When a setting value check such as a value check or a relative value check is performed, it is determined that the setting is incorrect and an alarm is output. In that case, it is sufficient to perform the setting again and rewrite the incorrect setting value of the first storage circuit to the correct setting value.

However, if the transfer switch is pressed while the erroneous settings are being reset, or if an erroneous operation is performed, all the erroneous setting values written in the first memory circuit are transferred to the second memory circuit. It will be transferred to the circuit. Therefore, the protection control device performs protection calculations using the incorrectly set value that is transferred to the second storage circuit and stored, resulting in the device malfunctioning or malfunctioning. This poses a major problem in the operation of the protection control device and greatly reduces the reliability of the device, and is a serious drawback in the conventional protection control device.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and its purpose is to prevent writing of incorrect setting values when changing settings in a protection control device equipped with a setting device using two memory circuits for storing setting values. Even if you accidentally perform a transfer operation when
It is an object of the present invention to provide a protection control device that is capable of performing protection calculations that are not transferred and reach obsolete specified values.

[Summary of the invention]

In order to achieve the above object, the present invention includes first and second storage circuits that store final setting values for protection control calculations;
means for writing a set value into the first memory circuit; means for transferring the contents of the first memory circuit to the second memory circuit; an arithmetic processing section that performs protection control calculations using input information; a set value check means that checks whether the set value written in the first storage circuit is defective; In some cases, the first memory time mentioned above-
The present invention is characterized by comprising means for blocking transfer from the path to the second storage circuit.

[Embodiments of the invention]

An embodiment of the present invention shown in the drawings will be described below.

FIG. 1 shows in block form an example of the configuration of a protection control device according to the present invention.

In FIG. 1, reference numerals 1 and 2 indicate readable and writable first and second memory circuits (RAM
:Random Access Memory), and normally the first storage circuit 1 stores the new setting value after the setting change, and the second storage circuit 2 stores the old setting value before setting. 5 is a write signal S for writing the setting value of the setting circuit 4 to a predetermined address in the first storage circuit 1.
A write switch 6 outputs 1, and a transfer switch 6 outputs a transfer request signal S2 when transferring the storage contents of the memory circuit 1 to the second memory circuit 2.

Further, 3 is an address control circuit for controlling writing/reading of the first and second memory circuits 1 and 2, and 7 is a master address control circuit.
This is an arithmetic processing unit composed of digital arithmetic devices centered on a central processing unit such as a microcomputer.

When writing a set value, this address control circuit 3 receives a write signal S1 and outputs a write signal W1 and its address value for writing the set value into the first storage circuit 1, and writes the set value into the first memory circuit 1. When transferring from the memory circuit 1 to the second memory circuit 2, in response to the transfer permission signal S9 output from the arithmetic processing unit 7, a read signal R for reading the set value of the first memory circuit 1, and A write signal W2 for writing the set values into the memory circuit 2 and their address values are output.

These address buses are connected to the first . It is output to the second storage circuit 1.2. Also,
The transfer permission signal S9 is outputted from the arithmetic processing section 7 to the address control circuit 3 only when the arithmetic processing section 7 receives the transfer request signal S2 and performs the above-mentioned setting value check, and the result is good. Since this address control circuit 3 is already well known in the published patent publication JP-A-56-1726J, etc., its details will be omitted here.

Note that the address value when writing the setting value to the first memory circuit 1 differs depending on the element to be set, and the address value is different depending on the element to be set.
The settings are made using an address setting circuit such as a digital switch provided inside the address setting circuit.

When the arithmetic processing unit 7 reads the contents of the first storage circuit 1 or the second storage circuit 2, the arithmetic processing unit 7 sends a request signal S3 for reading and its address value.
It is output to the address control circuit 3 via the address bus S8. Then, when reading is possible for the first storage circuit 1 or the second storage circuit 2, the read signal R1 or the read signal R2 and their address values are outputted from the address control circuit 3.

Further, when reading is not possible, the address control circuit 3 outputs a standby signal S4 to the arithmetic processing section 2, and the read operation is made to wait until reading becomes possible. Writing, transfer, and reading of these set values are performed via data bus S7.

On the other hand, 8 is an alarm circuit for issuing an alarm to the outside when the above-mentioned setting value check result is defective, and is operated by the alarm signal S10 outputted from the arithmetic processing section 3. Reference numeral 12 denotes an input/output interface section (hereinafter referred to as "input/output interface section") for inputting input information subject to protection control (for example, digital data such as power system voltage and current, external device information, etc.) and outputting protection calculation results to the outside. (referred to as external) is connected to the arithmetic processing unit 7 via a data bus 87'.

Next, the operation of the protection control device configured as described above will be explained.

First, FIG. 2 is a time chart showing the state of writing a set value to the memory circuit 1 and reading the set value from the first memory circuit 1 to the arithmetic processing unit 7 in FIG. In FIG. 2, a is the write signal S, b is the request signal S3,
c is the write signal W, d is the read signal R1, e is the write signal W2, f is the address bus S8, and g is the address bus S.
5 and h indicate the states of each signal on the address bus S6, respectively.

First, the address value of the element to be set is set in the address setting circuit in the address control circuit 3, and the setting value is set in the setting circuit 4. Now, the address setting value at that time is IA1''. Then, when the write switch 5 is turned on, the write signal S1 as shown in a is generated, and at the same time the address value of the address bus S5 is changed as shown in g. A1". Assuming that this time is tl, a write signal W1 is outputted from the address control circuit 3 to the storage circuit 1 at the same time tl as shown by C. Therefore, the first memory circuit 1 has °゛A
The setting value of the setting circuit 4 is transferred to the data bus S at the address “l”.
7. Also, change the address setting value to 'A2
#, and in exactly the same way, the 7th address “A2” of the first memory circuit 1
The setting value is written to #.

The above is the operation when writing the set value into the memory circuit 1. Next, the operation when the arithmetic processing section 7 reads the set value from the first memory circuit 1 will be described. The arithmetic processing section 7 outputs to the address control circuit 3 a request signal S3 as indicated by b and an address value S8 corresponding to the set value to be read as indicated by f. If this time is t3, the first memory circuit 1
When it is possible to read υ, a read signal R1 as shown by d is outputted from the address control circuit 3 to the storage circuit 1 at the same time t3. Therefore, the set value stored at the address "A," of the first storage circuit 1 is read by the arithmetic processing unit 7 via the data bus S7.

Similarly, the required number of set values are read up to the address "An". These set values read are
Generally, it is stored in a data memory (not shown) in the arithmetic processing section 7. Note that when the first memory circuit 1 is unreadable,
Needless to say, the address control circuit 3 outputs the standby signal S4 to the arithmetic processing unit 7, and the process waits until it becomes ready for reading. Furthermore, it is clear that the set value of the second storage circuit 2 can be read in the same manner. That is, the request signal S3 and the address bus S8 are used to read the set value of the second storage circuit 2 from the address control circuit 3)' The signal R2 and its address value are outputted via the address bus S6. You can do it like this. Through the above-described operations, a set value is written to or read from the first storage circuit 1.

Next, checking of these set values written in the first memory circuit 1 and transfer to the second memory circuit 2 will be described.

Figure 3 shows that the results of 1. these setting value checks are good and the 2.
2 shows a timing chart when a set value is transferred to the storage circuit 2 of FIG.

In FIG. 3, a is the transfer request signal S2, b is the processing content in the arithmetic processing unit 7, C is the transfer permission signal S9, d is the write signal Wl, e is the read signal R, and f is the write signal W.
2, g is address bus S5, h is address bus 86, l
indicate each state of the alarm signal 810, respectively.

First, when the transfer switch 6 is turned on, a transfer request signal s2 is output to the arithmetic processing section 7 as shown in a. When the transfer request signal S2 is inputted to the arithmetic processing unit 7, the set value of the first storage circuit 1 read as shown in FIG. Check the setting value. This set value check is to determine whether the set value written in the first memory circuit 1 is an appropriate value for the protection control device, and as mentioned above, absolute value check, relative value check, etc. will be carried out. Absolute value checking is a check for each element to see if the written setting value is within a specified range.
Relative value checking is a relative check for each element to see if it has a predetermined magnitude relationship with the set value of another element. If the results of these setting value checks are good, then the setting value written in the first memory circuit 1 is not an erroneous setting, and the address control circuit is sent from the arithmetic processing unit 7 as shown in C. 3, a transfer permission signal S9 is output. Note that the alarm signal sio is not output.

On the other hand, when the address control circuit 3 receives the transfer permission signal S9, it outputs a read signal R for sequentially reading out the set value of the first storage circuit 1, as shown by e and f, and a second
A write signal W2 is outputted to sequentially write the set values into the memory circuit 2 of. These read signal R1 and write signal W2 are output for a period T required to transfer all the setting values stored in the first storage circuit 1 to the second storage circuit 2.

At the same time, as shown by g and h, all address values A1 to An of the setting values stored in the first storage circuit 1 are
All address values B to be written to the first and second memory circuits 2
l-Bn are output via addresses 85 and 86, respectively. Therefore, the address A1 of the first memory circuit 1
The set value stored in ~An is stored in the second storage circuit 2.
- It will be transferred to addresses Bl-Bn. At this point, all the setting work has been completed, and the arithmetic processing section 7
performs a protection operation using the correct set value of the second storage circuit 2 and the input information input from the local section 12 via the data bus 87'. The result of the protection operation is output from the h section 12 to the outside via the data bus 87'.

Next, a case where erroneous setting is performed will be explained with reference to FIG. In FIG. 4, IL-1 is a timing chart showing the same operations as a-1 in FIG. Similarly to the above, 2, by turning on the transfer switch 6, the transfer request signal S2 is sent to the arithmetic processing unit 7 as shown in pa.
is output to. In the arithmetic processing unit 7, this transfer request signal S
If 2 is input, an absolute value check and a relative value check of the set value are performed during the period T2 shown in b. Then, there is an error '1' in the setting value written in the first memory circuit 1.
If the result of either or both of the absolute value check and relative value check is defective, the transfer permission signal S9 is not output from the arithmetic processing unit 7 as shown in C. Then, as shown in j, the alarm signal 810 is sent to the alarm circuit 8.
is output to alert the outside that the setting is incorrect.

Further, since the transfer permission signal S9 is not input to the address control circuit 3, the write signal W, the read signal R, the write signal W2, the address bus S5. None of S6 will be output. Therefore, the incorrect setting value written in the first memory circuit 1 is stored in the second memory circuit 2.
will not be forwarded to. Incidentally, in the case where an erroneous setting is performed in this way, if the correct setting value is rewritten in the first storage circuit 1 by resetting, the transfer will be performed as shown in FIG. 3.

With the operation described above, even if the transfer switch 6 is turned on by mistake with an incorrect setting value written in the first memory circuit 1, the old setting value of the second memory circuit 2 is used to protect the device. It becomes possible to perform calculations.

Next, other embodiments of the present invention will be described.

FIG. 5 shows another configuration example of the protection control device according to the present invention. In FIG. 5, the same parts as in FIG. I will only describe the parts.

That is, in FIG. 1, the transfer request signal S2 is
is input, and after checking the set value, the transfer permission signal S9 is output to the address control circuit 3 to perform the transfer. Write signal W2 of memory circuit 2 of No. 2
It is designed to control.

In FIG. 5, 9 is a delay circuit for delaying the transfer request signal S2 by a predetermined time, 10 is a NOT (logic inversion) circuit for inverting the logic of the alarm signal 810, and 11 is a write circuit that uses the output of this NOT circuit 10. This is an AND (logical product) circuit for controlling the signal W2.

Next, the operation shown in FIG. 5 will be explained using FIG. 6. FIG. 6 shows a timing diagram when the check result of the setting value written in the first storage circuit 1 is good and the setting value is transferred to the second storage circuit 2. .

In the figure, a is the transfer request signal S2, b is the output of the delay circuit 9, C is the processing content of the arithmetic processing unit 7, and d is the read signal R.
1, e is the light signal W2, and f is the alarm signal 810.

g is the output of AND circuit 1, h is address bus S5, i
indicate the status of each signal on the address bus S6.

First, by turning on the transfer switch 6, the transfer request signal S2 is transmitted to the arithmetic processing unit 7 and the delay circuit 9 as shown in a.
is output to. In the arithmetic processing unit 7, this transfer request signal S
2 is input, the setting value of the first memory circuit 1 is
As shown in C, the set value is checked during the period T1.

Furthermore, as shown in b, the delay circuit 9 receives the transfer request signal S.
2 is input, an output is generated after a delay of 1 ri, which is the time required for checking the setting value, and this is input to the arithmetic processing section 7. Note that it is clear that the delay circuit 9 can be easily constructed using a well-known time-limited operation circuit, a time-limited return circuit, etc., so a description thereof will be omitted here. When the unit 7 inputs the read signal R1 for sequentially reading out the setting values of the first storage circuit 1 as shown by d and f in the same way as in FIG. A write signal W2 for sequentially writing the data is output during the period T! required for transfer. However, the write signal W2 is input to the storage circuit 2 via the AND circuit 11. .

As shown by l, all address values A1 to knz of the setting values stored in the first storage circuit 1 and the second storage circuit 2
All address values Bl to Bn to be written to address buses S5. It is output via S6. Further, if the arithmetic processing unit 7 checks the set value of the first storage circuit 1 during the period Ti and the result is good, the alarm signal S'10 is not output as shown by f. Therefore, since the alarm signal 810 is inverted by the NOT circuit 10 and inputted to the AND circuit 1, the output of the AND circuit 11 becomes the same signal as the write signal W2, as shown by g, and this is sent to the second storage circuit 2. is input. Therefore, the set value stored at the address At-An of the first storage circuit 1 is transferred to the addresses B1 to BTl of the second storage circuit 2.

Next, a case where erroneous setting is performed will be explained with reference to FIG. In FIG. 7, a-1 is a timing/guchiard diagram showing the same operations as a-1 in FIG. Similarly to the above, by turning on the transfer switch 6, the transfer request signal S2 is outputted to the arithmetic processing section 7 and the delay circuit 9 as shown in a. Then, in the arithmetic processing section 7, as shown in C, the period T! In addition, the delay circuit 9 delays the transfer request signal S2 by a time 'rt and outputs it to the address control circuit 3. Then, from the address control circuit 3, as shown in d, s, h, i, as described above,
Read signal R1, write signal W2, address value person 1~A
nN address values 81 to Bn are output, respectively.

Then, if the result of checking the set value of the first storage circuit 1 during the period Tl is defective, an alarm signal 810 is outputted as indicated by f. Therefore, the alarm circuit 8 issues an alarm to the outside that the setting is incorrect. Additionally, since this alarm signal 810 is also input to the AND circuit 11 via the NOT circuit 10, no output is generated in the AND circuit 1 as shown in g. Therefore, since the write signal 2 is not input to the second memory circuit 2, the set value is not written, that is, no transfer is performed, and in the case of FIG. 1, exactly the same effect can be obtained. become.

Note that the present invention is not limited to the above embodiments.

(In the above explanation, we have described the case where both the absolute value check and the relative value check are performed in period T2.
The absolute value check is not limited to this, but the absolute value is checked every time the set value is written into the first memory circuit 1, and only the relative value is transferred after the switch 6 is turned on. You may also check it. Note that at this time, it goes without saying that the transfer permission signal and the alarm signal are output only when both checks are positive.

(2) In the above description, the first memory circuit 1 and the second memory circuit 2 are readable and writable memory circuits (RA).
The case where M) was used was described. This RAM is
Due to its nature, when the power is lost, the memory content disappears, but if the memory content, that is, the setting value, needs to be preserved even if the power is lost, the memory content can be read and written, and the memory content can be preserved even if the power is lost. RAM with non-volatility that never disappears
, for example MNOS (Metal N1trlde
OxidsSeml, conductor ) -R
AM may be used. This MN6S-RAM is described in detail in the above-mentioned Japanese Patent Laid-Open Publication No. 1762-1983, and is already a well-known method, so it will not be described in detail here, but this MNOS-RAM is If used in the memory circuits 1 and 2, the set value is preserved even if the power supply is lost, so that a more advantageous protection control device can be obtained.

(3) In the above explanation, the first and second memory circuits I
The case has been described in which the arithmetic processing unit 7 reads the set values stored in the arithmetic processing unit 7 and 2 and stores them in the data memory in the arithmetic processing unit 7. If the response speed of the first and second memory circuits 1 and 2 is extremely slow, the memory contents of the first and second memory circuits 1 and 2 are stored in the arithmetic processing unit 7 using the idle time of the arithmetic processing unit 7. A so-called DMA (direct memory access) method may also be used in which the data is transferred to a data memory within the memory. This DMA method is based on the above-mentioned “Unexamined Japanese Patent Publication No.
1762J, and is already a well-known method, so it will not be described in detail here, but it includes writing the set value to the first memory circuit 1, checking the set value, and writing the set value from the first memory circuit 1. The method of the present invention is applied to transfer the set value to the second memory circuit 2, and the DMA method is used to read the set value from the first memory circuit 1 and the second memory circuit 2 into the arithmetic processing unit 7. By applying this, a protection control device that can improve calculation efficiency can be obtained.

〔Effect of the invention〕

As explained above, according to the present invention, the first and second two
In a protection control device that has a setting value using two memory circuits, even if a transfer operation is performed by mistake with an incorrect setting value written in the first memory circuit, the second memory circuit The erroneous settings are not transferred and it is possible to perform protection control calculations using the old settings stored in the second memory circuit, providing highly reliable protection that is extremely advantageous for device operation. Control equipment can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the protection control device according to the present invention, FIG. 2 is a timing chart diagram illustrating writing of the setting value in FIG. 1 and reading it to the arithmetic processing section, and FIG. and FIG. 4 is a timing chart diagram explaining the checking and transfer of the setting value in FIG.
FIG. 5 is a block diagram showing another embodiment of the protection control device according to the present invention, and FIGS. 6 and 7 are timing charts illustrating checking and transfer of the set value in FIG. 5. 1.2...Memory circuit, 3...Address control circuit, 4
... Arithmetic processing unit, 5... Write switch, 6... Transfer switch, 7... Arithmetic processing unit, 8... Alarm circuit,
9...Delay circuit, 10...Knot circuit, 1...
AND circuit, 12... input/output interface section. Figure 1 Figure 2 - Figure 3 i Figure 4; d: Q [ = Figure 5 Figure 6

Claims (1)

[Claims] a first and a second memory for storing set values for protection control calculations;
a memory circuit, means for writing a set value into the first memory circuit, means for transferring the contents of the first memory circuit to the second memory circuit, and a memory circuit of the Ml, a second memory circuit; an arithmetic processing unit that performs protection control calculations using the contents and input information of an external source; a set value checking unit that checks for defects in the set value written in the first storage circuit; and the set value check unit. If the set value is bad as a result, the first
A protection control device comprising means for blocking transfer from the storage circuit to the second storage circuit.