JPH0336650A - Memory protecting system - Google Patents

Abstract

PURPOSE:To prevent data from being destroyed by program error during the transfer of the data by providing a preferential protection key in a data reception buffer on a memory. CONSTITUTION:A read signal for accessing a memory protection key 3 and an address signal are sent from a controller 1 to a memory 2 according to a DMA transfer request and the memory protection key is outputted to a data bus 10. Simultaneously, the controller 1 sends the address signal and a write signal to a data write buffer 4 and outputs a memory write key to a signal line 11. When the result of a key AND 12 of the buses 10 and 11 is '1', the buffer 4 is opened and the memory 2 is accessed. At the time of writing from the controller 1 to the normal buffer of the memory 2, the output of the AND 12 is '0' and the buffer is not opened. Then, the memory 2 can not be accessed. At such a time, the memory protection key of the bus 10 and the write key of the signal line 11 are inputted to a NAND circuit 14 and AND circuit 15 and an interruption signal can be outputted through an interrupting circuit 16 to a CPU. Thus, the data are prevented from being destroyed and the program error can be searched by the information of the interruption signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention prevents a data transfer buffer from being destroyed due to a program error during data transfer from an input/output device to a memory.

[Conventional technology]

The conventional method, as described in Japanese Patent Application Laid-open No. 191950/1983, is to DM any data stored in the memory.
This is to protect it from access by the A controller.

[Problem to be solved by the invention]

In the data transfer method, which uses the system bus to directly transfer data between input/output devices and memory without CPU intervention, two devices are running in parallel while data is being transferred from the input/output device to memory. Even if the data in the transfer liquid has already been destroyed by the program, it is difficult to determine whether the cause is a program error or an abnormality in the data transfer operation. Although the method disclosed in Japanese Patent Application Laid-Open No. 62-191950 can protect a specific memory area against DMA operation abnormalities, this is due to program errors.

Destruction of the DMA transfer area cannot be detected.

An object of the present invention is to prevent data from being destroyed due to program errors during data transfer.

[Means to solve the problem]

The above object is achieved by providing a priority protection key in the data transfer buffer on the memory and prohibiting writing when a write request is generated from a source other than the data transfer controller.

[For production]

There are priority and non-priority classes of protection keys assigned to each fixed memory space, and write permission/prohibition is determined by comparing the write key at the time of a write request with this protection key. By setting a priority protection key in the data transfer buffer above, and using the priority write key when writing data from the data transfer controller, and performing non-priority writing when writing data from a general program, it is possible to prevent errors in the program from occurring. Even if a write request occurs in the data transfer buffer, the request can be prohibited due to a mismatch between the write key and the protection key.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
FIG. 1 is a partial block diagram showing the configuration of a DMA system according to an embodiment of the present invention. 1 is an MA controller that can directly access memory similar to the CPU, and 2 is a DMA controller.
This storage device 1 (memory) 2, which is a storage device (memory) that can be accessed by the controller l, is provided with memory protection keys 3 at regular intervals, and when the storage device (memory) l is initialized, it is stored in a normal buffer. 'o' data is written in the buffer to be written by DMA, and '11' data is written in the buffer to be written by DMA. 4 is a buffer circuit which connects the internal address bus 5, the WRITE signal line 6, the external address bus 7 and the external WRITE signal line 8. It has the function of controlling the connection of 9 indicates the memory protection key read out to the data bus 10 through the READ signal line 13 and the address bus 14, and the memory write key outputted through the signal line 11.
) This is an enable signal line output by the circuit 12, and serves as a manual control signal for the buffer circuit 4. 13 is an interrupt circuit that connects the memory protection key of the data bus 10 and the memory write key of the signal line 11 with a NAND circuit 14;
The output of Elj path 15 is input.

Next, the operation of the embodiment circuit of the present invention will be explained with reference to FIG. When a DMA transfer request occurs, the DMA controller 1 first transfers the storage device i! READ signal line 1 to access memory protection key 3 to (memory) 2
A READ signal and an address signal are sent to the address bus 14 and address bus 14, respectively.

As a result, a memory protection key is output onto the data bus 10. Also, I) MA controller 1 simultaneously sends the data write buffer address signal to address bus 5, WRI
WRITE signal on TE signal line 6.

And a memory write key is output to the signal line 11.

The AND circuit 12 inputs the memory protection key of the data bus 10 and the memory write key of the signal line 11.

If the AND result is high level (1), the buffer circuit 4 is opened by outputting an enable signal to the buffer circuit 4 via the enable signal line 9, and the address bus 5 and WRITE signal line 6 are connected to the external address bus. 7
and external WRITF.

A storage device connected to signal line 8! (Memory) 2 can be accessed. On the other hand, from the DMA controller 1 to the storage device f! (
When attempting to write data to the normal buffer of memory) 2, the output result of the memory protection key of the data bus 10 input to the AND circuit 12 and the memory write key of the signal line 11 becomes low level (0), No enable signal is output to the buffer circuit 4 via the enable signal line 9;
Therefore, the buffer circuit 4 is not opened and the DMA controller 1 is in the storage device f! (Memory) 2 cannot be accessed, and at this time, by inputting the memory protection key of the data bus 10 and the memory write key of the signal line 11 to the NAND circuit 14 and the AND circuit 15, the 1 interrupt circuit 16
An interrupt signal can be output to the CPU via.

According to the above-mentioned first embodiment, the storage device due to an error in addressing the data write buffer in the DMA method! It is possible to prevent data corruption on (memory), and it is recommended to search for program errors using the information of the interrupt signal.

〔Effect of the invention〕

As described above, according to the present invention, when data corruption in the data transfer buffer occurs during data transfer from an input/output device to memory using the DMA method, it is possible to determine whether it is due to a program error or other factors. It is possible to make the determination at a glance, and the time required to analyze the cause of data corruption can be significantly shortened.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a system employing a DMA method, showing one embodiment of the present invention. 1...DMA controller, 2...memory, 3...
・Memory protection key, 4...Buffer circuit, 5, 7...
Address bus, 6, 8, 9, 10, 11.13...Data bus, 12.15...AND circuit, 14...N
AND circuit, 16... interrupt circuit.

Claims (1)

[Claims] 1. During data transfer from the input/output device to the memory, by providing a memory protection key that protects the data receiving buffer on the memory with priority over normal memory, it prevents the data receiving buffer from being destroyed by a program running in parallel. A memory protection method that is characterized by: