JPH0390946A - Storage device - Google Patents

Abstract

PURPOSE:To detect an access given to an area secured at an optional point with the optional width set previously by deciding whether the area received an access based on the contents of an area defining memory is identical with a detected area or a non-detected area. CONSTITUTION:Plural areas are secured via a control circuit 5 in response to the prescribed storage units of a storage element 7. Then it is decided whether the area received an access is identical with a detected or non-detected area based on the contents of an area defining memory 6 which defines the detected and non-detected areas. The circuit 5 sends an address signal E and a control signal F to the element 7 based on an address input signal A and a control information input signal B received from a computer main body and performs an access via a data signal G. At the same time, the circuit 5 sends the signal E to the memory 6 to read the memory 6. Thus it is possible to detect an access given to an area secured at an optional point with the optional width set previously.

Description

DETAILED DESCRIPTION OF THE INVENTION "Industrial Field of Application 1 This invention is applicable to a total of 3F using multiple stack areas, for example.
, relates to storage devices for machine systems.

In particular, it relates to a storage device that can detect access to a preset area.6 [Prior Art] In a processing device using a storage device, in particular, one or more stack areas are set in the storage device. In the process performed by
It is necessary to check whether access to the storage device is within a certain area.

In order to realize this check function, conventional devices use hardware methods such as a storage protection mechanism, or software methods that check the memory address on each access, as a problem on the side of controlling the storage device. Checking.

In a typical computer system as a processing device that uses a storage device, there is no special area detection function for arbitrary areas, but for example,
Edited by Akira Ninomiya, published by Ohmsha, June 25, 1985, No. 45
Memory protection is achieved by methods such as the (multiple) virtual memory method, boundary register method, protection bit method, protection key method, ring protection method, qualified address method, etc. listed on pages 55 to 55. Using the functions of these methods, areas are checked by a method that detects access to areas for which use is not permitted as an error.

[Problems to be Solved by the Invention] ] In conventional storage devices such as dual storage devices, this is treated as a memory protection problem on the control side, so virtual storage methods, protection bit methods, protection key one-way methods, ring protection method,
Methods such as the qualification access method require complex and large-scale circuits, and usually have the problem of not being able to detect detailed areas.

Further, in the boundary register method, since a boundary register is required for each area, there is a problem in that the circuit size for detection becomes large when area detection is performed for a number of areas.

Furthermore, when area detection is performed by software, a check operation is required each time a storage device is accessed, which creates overhead and reduces execution performance.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a storage device that can detect access to a preset arbitrary location and arbitrary width area.

[Means for Solving the Problems] A storage device according to the present invention includes the following means.

(i) A region definition memory in which a plurality of regions are provided corresponding to a predetermined storage unit of a storage element, and a detection region and a non-detection region are defined.

(ii) A control circuit that determines whether the accessed area is the detection area or the non-detection area based on the contents of the area definition memory.

[Operation] In the present invention, a plurality of areas are provided by the control circuit corresponding to a predetermined storage unit of a storage element, and based on the contents of an area definition memory defined as a detection area and a non-detection area. Then, it is determined whether the accessed area is the detection area or the non-detection area.

[Embodiment] The configuration of an embodiment of the present invention will be described with reference to FIG.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, one embodiment of the present invention includes signal lines (1), (2>, (3)) for address input signals, control information input signals, data input/output signals, and status information output signals. (
4), the control circuit (t1) connected to the computer main body at t'
5) and an area definition memory whose input side is connected to the control circuit (5) by a signal line (8) for an address signal and whose output side is connected to the control circuit (5) by a signal line (11) for an area determination signal. (6) and a memory element (7) connected to the control circuit (5) by signal lines (8), (9) and (10) for address signals, control signals and data signals. There is.

The area definition memory (6) is a memory that can read one bit at a time, and is a read-only semiconductor memory (6).
ROM>. The storage element (7>) is constituted by a readable and writable semiconductor memory (RAM).

Next, the operation of the above-mentioned embodiment will be explained.

In one embodiment of the present invention, a control circuit (5) receives an address input signal A and a control information input signal B from the computer main body, and receives a status information output signal n indicating matters such as access completion.
Output and respond. The control circuit (5) also transfers data C that is read and written from the computer main body.

A control circuit (5) sends an address signal E and a control signal F to a storage element (7) in accordance with an address input signal A and a control information input signal B from the computer main body, and performs access via a data signal G. At the same time, the address signal E is sent to the area definition memory (
6) and reads out the area definition memory (6).

It is assumed that in this area IL (If definition memory (6)), 1° is written in advance at the address corresponding to the area where access is to be detected, and "0" is written in the other areas.

The area definition memory (6) has a storage element (7) and an address signal E.
Therefore, when Chishikore outputs "1, it indicates that the detection area has been accessed.The area determination signal 4, which is the output of the area definition memory 6), is connected to the signal line (■ 1) to the control circuit (5).

The control circuit (5) reads the area definition memory (6> in parallel with the access to the storage element (7). When the access to the storage element (7) is completed, the control circuit (5)
reads the contents of the region determination signal H, and notifies the computer main body of the end of access and the result of region determination by means of a status information output signal.

The region definition memory (6) does not need to be a read-only memory, but can also be a readable and writable memory element. Example of this case (other embodiments of this invention)
is shown in Figure 2.

FIG. 2 is a block diagram showing another embodiment of the invention.

In FIG. 2, another embodiment of the invention includes an area definition memory consisting of a readable and writable memory element (RAM) instead of the area definition memory (6) of the dual series one embodiment. (6^> is used.

Therefore, in this other embodiment, the area definition memory (6^)
Adds a write operation to . The control circuit (5) specifies the address of the area definition memory (6^) to be set by using the address input signal ``,'' and transmits the contents to be written using the data input/output signal C. A write instruction to the area definition memory (6^) is given by the control information input signal B. The control circuit (5) controls the area definition memory (6^) using the area definition control signal J, and writes to the area definition memory (6^) by transmitting the write content using the area definition data input/output signal K. . Memory element (7)
Normal access to the area definition memory (6^)
By controlling the readout state, area detection is performed in the same manner as in the embodiment shown in FIG.

Since each embodiment of the present invention is equipped with the area definition memories (6) and (68) as described above, it is possible to monitor input address and other control information by adding only a small amount of logic. This has the effect of being able to detect access to any preset area of any number and size.

In each of the embodiments described above, the area definition memory (6), <6^
) handles 1-bit information, but it may also handle multiple bits. In addition, the information written to the area definition memory (6), <6^) for detection uses "1" for the detection area and "O" for other areas, but the reverse is true. Combinations may also be used. Furthermore, when the area definition memories (6), (6^>) have multiple bits of information, any data pattern can be assigned to the detection area and non-detection area.

Furthermore, area definition memories (6) and (6^) are storage elements
7) and by completely sharing the address signal E, it was shown that area determination information could be obtained for each storage unit in the storage device, but area definition memories (6) and (6^) are A part of the address signal E given in (7) may be shared. In this case, the area determination information is set collectively for a plurality of storage units.

In addition, in each of the above embodiments, the area definition memory (6>, (6^
) and the storage element (7) are operated simultaneously in parallel by the control circuit (5), but they can also be accessed sequentially rather than simultaneously. For example, first,
By reading the area definition memories (6) and (6^), it is determined whether the access to the storage device is related to the defined area.

This determination result is output as a status information output signal by the control circuit (5), and the computer body determines whether to perform access to the storage element (7), cancel it, or access the memory element (7) according to this status information output signal. A decision is made to switch to a different access than specified, and the result is communicated to the control circuit (5) through the control information input signal B.

Further, in each of the above embodiments, separate elements were used for the control circuit (5), area definition memories (6), (68), and storage element (7), but some or all of these may be integrated into one It goes without saying that the intended purpose can be achieved even if integrated as a semiconductor chip.In the above explanation, we have talked about the case where it is used as a storage medium in semiconductor memory, but it can also be used in other formats, such as disk devices. Needless to say, it can also be used.

[Effects of the Invention] As explained above, the present invention provides an area definition memory in which a plurality of areas are provided corresponding to a predetermined storage unit of a storage element, and a detection area and a non-detection area are defined. , and a control circuit that determines whether the accessed area is the detection area or the non-detection area based on the contents of this area definition memory, so that access to an area of any preset location and width can be detected. It has the effect of being able to

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the invention, and FIG. 2 is a block diagram showing another embodiment of the invention. In the figure, <5>... Control circuit, (6>, (68)... Area definition memory, (7)
... It is a memory element. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] An area definition memory in which a plurality of areas are provided corresponding to a predetermined storage unit of a storage element and is defined as a detection area and a non-detection area, and an area accessed based on the contents of this area definition memory are as described above. A storage device comprising a control circuit that determines whether the area is a detection area or a non-detection area.