JP2904266B2 - Memory connection controller that can cope with bus degradation - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory connection control device for controlling connection of two memories corresponding to a dual bus one-to-one.

[0002]

2. Description of the Related Art Conventionally, an access to a storage device of a computer is sometimes made using a dual bus. In such a case, an address / command control LSI, a data control LSI, and a memory are often connected to each bus independently.

[0003] Assuming that one of the dual buses has failed, Japanese Patent Laid-Open Publication No. Sho 62-8832 has proposed a countermeasure against this.
A bus mode control bit is provided on the bus, and the data control LS
I. An attempt is made to control the input / output of the bus with an exclusive OR signal with the I / O buffer control signal of the address / command control LSI.

[0004]

However, when a memory is independently connected to each bus, if one of the dual buses fails, the memory corresponding to the failed bus cannot be used. There is a disadvantage that.

[0005] Therefore, an object of the present invention is to control a memory corresponding to one of the dual buses through the other normal bus even if one of the dual buses fails, so as to cope with the failed bus. It is an object of the present invention to provide a memory connection control device which can use a memory which has been used.

[0006]

[0007]

According to the present invention SUMMARY OF], the memory connection control device for controlling the connection of the first and second memory corresponding one-to-one to the first and second bus, said first A first address / command control LSI connected between a bus and the first memory for controlling an address / command for the first memory; Connected to the first address / command control LSI, and connected to the first address / command control LSI by an instruction from the first address / command control LSI.
A first data control LSI that controls data for the second memory, and a second data control LSI that is connected between the second bus and the second memory and controls an address / command for the second memory. Address / command control LSI
And connected between the second bus and the second memory and connected to the second address / command control LSI, and the second address / command control LSI in response to an instruction from the second address / command control LSI. A second data control LSI for controlling data to a memory, an inter-LSI address command bus connecting the first and second address / command control LSIs, and the first and second data control LSIs An inter-LSI data bus connected between them,
When one of the first and second buses fails, the first and second address / command controls L through the inter-LSI address command bus.
An address / command is transferred between SIs, and data is transferred between the first and second data control LSIs via the inter-LSI data bus. Can be

Further, according to the present invention, in a memory connection control device for controlling connection between first and second memories which correspond to first and second buses on a one-to-one basis, the first bus and the first bus are controlled. Address command control means for controlling an address command for the first memory, connected between the first bus and the first memory, and First data control means connected to the first address / command control means for controlling data for the first memory in accordance with an instruction from the first address / command control means; and A second address / command control means connected between the second memory and the second memory, for controlling an address / command for the second memory; Connected and coupled to said second address command control means, said second address
A second data control unit for controlling data to the second memory in accordance with a command from the command control unit; The first and second addresses when one of the buses fails.
Address / command transfer means for transferring an address / command between command control means, and one of the first and second buses connected to the first and second data control LSIs; And a data transfer means for transferring data between the first and second data control means when a failure occurs.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A memory connection control device according to an embodiment of the present invention will be described with reference to FIG. FIG.
, A main storage device 3 is connected to a dual bus, that is, the first and second buses 1 and 2. The main memory 3 is a first bus corresponding to the first and second buses 1 and 2 on a one-to-one basis.
And second memories 4 and 5.

The main storage device 3 further includes a first address / command control LSI 6, a first data control LSI 7,
A second address / command control LSI 8 and a second data control LSI 9 are included. The first address / command control LSI 6 is connected between the first bus 1 and the first memory 4 and controls an address / command for the first memory 4. The first data control LSI 7 controls data for the first memory 4 in accordance with an instruction from the first address / command control LSI 6. The second address / command control LSI 8 is connected between the second bus 2 and the second memory 5 and controls an address / command for the second memory 5. Second data control LSI
Reference numeral 9 denotes data for controlling the data in the second memory 5 according to an instruction from the second address / command control LSI 8.

Further, the first and second address / command control LSIs 6 and 8 include an inter-LSI address command bus 1.
1 are connected to each other. The first and second data control LSIs 7 and 9 are connected to each other by an inter-LSI data bus 12.

First, the operation when the first and second buses 1 and 2 are in a normal state will be described. When writing data to the first memory 4, a write command, an address, and write data are sent through the first bus 1. The write instruction, address and write data are received by the first address / command control LSI 6 and the first data control LSI 7. And a first address / command control LSI
6 and the first data control LSI 7 send the address and the write data to the first memory 4, respectively. In response,
The first memory 4 performs a write operation of write data.

When reading data from the first memory 4, a read command and an address are sent through the first bus 1. The read command and the address are received by the first address / command control LSI 6. Then, the first address / command control LSI 6 stores the address in the first memory 4.
To send to. In response to this, the first memory 4 performs a read operation to transfer read data to the first data control LSI 7.
To send to. The first data control LSI 7 outputs read data to the first bus 1.

When data is written to or read from the second memory 5, the second bus 2, the second second address / command control LSI 8, and the second data control LSI 9 are used. The same operation as in the case of the first memory 5 described above is performed.

Next, a case where the second bus 2 has failed will be described as an example. In this case, the first memory 4
The operations of writing and reading data to and from the second memory 5 will be described only.

When writing data to the second memory 5, a write command, an address and write data for the second memory 5 are sent through the first bus 1. The write instruction and the address and the write data correspond to a first address / command control LSI 6 and a first data control LSI 7, respectively.
Received by

When receiving a write instruction and an address for the second memory 5, the first address / command control LS
I6 sends a write command and an address to the second address / command control LSI 8 via the inter-LSI address command bus 11. At the same time, the first address / command control LSI 6 controls the first data control LSI 7
An instruction to output write data is sent to the inter-LSI data bus 12.

In response to the write command and the address, the second address / command control LSI 8 controls the second data control LS
At I9, an instruction to receive write data sent from the first data control LSI 6 is issued. In response to the command to output the write data, the first data control LSI 7 sends the write data to the second data control LSI 9 via the inter-LSI data bus 12.

As a result, the second address / command control LSI 8 and the second data control LSI 9 send address / write data to the second memory 5, respectively. In response, second memory 5 performs a write operation.

When data is read from the second memory 5, a read command / address for the second memory 5 is sent through the first bus 1. Read instruction / address is 1st
Is received by the address / command control LSI 6.

When receiving a read command / address for the second memory 5, a first address / command control LSI
Numeral 6 sends a read instruction / address to the second address / command control LSI 8 through the inter-LSI address command bus 11. The second address / command control LSI 8 sends the address to the second memory 5. In response, the second
Memory 5 performs a read operation. The read data read from the second memory 5 is stored in a second data control LSI 9
Sent to

Next, a second address command control LSI
8 issues a command to the second data control LSI 9 to output read data to the inter-LSI data bus 12. At the same time, the second address / command control LSI 8
A predetermined command is sent to the first address / command control LSI 6 through the inter-I address command bus 11. In response to the predetermined command, the first address / command control LSI 6 issues a command to the first data control LSI 7 to receive the read data sent from the second data control LSI 9.

The second data control LSI 9 sends read data to the first data control LSI 7 through the inter-LSI data bus 12. The first data control LSI 7 receives the read data and outputs it to the first bus 1.

First and second address command control LS
When passing an address command between I6 and I8,
First and second address command control LSIs 6, 8 and L
The address command bus 11 between SIs
Works as a command passing means. When transferring write data or read data between the first and second data control LSIs 7 and 9, the first and second data control LSI
The SIs 7, 9 and the data bus 12 between the LSIs together serve as data transfer means.

Incidentally, even when the first bus 1 fails,
As described above, the write and read operations can be performed on the first memory 4.

[0026]

According to the present invention as described above,
Even if one of the dual buses fails,
The memory operation can be performed without reducing the memory capacity.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a memory connection control device according to an embodiment of the present invention in relation to first and second buses.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 first bus 2 second bus 3 main storage device 4 first memory 5 second memory 6 first address / command control LSI 7 first data control LSI 8 second address / command control LSI 9 Second data control LSI 11 Inter-LSI address command bus 12 Inter-LSI data bus

Claims (2)

(57) [Claims] 1. A memory connection control device for controlling connection between a first memory and a second memory corresponding to a first bus and a second bus in a one-to-one correspondence, wherein a connection between the first bus and the first memory is provided. And a first address / command control LS for controlling an address / command for the first memory.
I, connected between the first bus and the first memory and connected to the first address / command control LSI, and the first address / command control LSI receives the first A first data control LSI that controls data for the second memory, and a second data control LSI that is connected between the second bus and the second memory and controls an address / command for the second memory. address·
A command control LSI, connected between the second bus and the second memory and connected to the second address / command control LSI, and in response to a command from the second address / command control LSI, A second data control LSI for controlling data for a second memory, an inter-LSI address command bus connecting the first and second address / command control LSIs, the first and the second An inter-LSI data bus connected between data control LSIs, and when one of the first and second buses fails, the first and second data buses pass through the inter-LSI address command bus. An address / command is transferred between the address / command control LSIs, and the first and the second devices are passed through the inter-LSI data bus. Memory connection controller being characterized in that to perform the transfer of data between two data control LSI. 2. A memory connection control device for controlling connection between a first memory and a second memory corresponding to a first bus and a second bus in a one-to-one correspondence, wherein a connection between the first bus and the first memory is provided. Address and command control means for controlling an address command for the first memory; and a first address and a first address connected between the first bus and the first memory. First data control means connected to command control means for controlling data to the first memory in accordance with an instruction from the first address / command control means; and second bus and second data control means. A second address / command control unit connected between the second bus and the second memory, the second address / command control unit being connected between the second bus and the second memory; A second data control means connected to a second address / command control means for controlling data to the second memory in accordance with an instruction from the second address / command control means; 2
And transfer of an address command between the first and second address / command control means when one of the first and second buses fails. Address / command transfer means for performing the first and the second data control, wherein the first and the second data control LSIs are connected to the first and the second data control LSIs when one of the first and the second buses fails.
And a data transfer means for transferring data between the data control means.