JP2000207235A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the storage contents of a memory from being destroyed by speedily resetting a CPU, when the CPU operates abnormally. SOLUTION: This processor 101 is equipped with a CPU 102 and memories 103 to 106 that the CPU 102 accesses, and a runaway write detecting circuit block 111 decides whether or not the CPU 102 is accessing an unused area in an accessible memory space according to chip select signals CS1 to CS7 outputted by an address decoder circuit block 108 and outputs a reset signal to the CPU 102, when the decision result is true to reset the CPU. The runway writing detecting circuit block 111 outputs the reset signal to the CPU 102, if the CPU attempts illegal writing to an EPROM 103 and a flash ROM 104.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus having a function of resetting a CPU when the CPU goes out of control.

[0002]

2. Description of the Related Art As a countermeasure for a case where a CPU (Central Processing Unit) constituting an information processing device runs away and performs an unexpected operation, a watchdog timer reset circuit (W
DT circuit). The WDT circuit performs a timer operation for time-up at a fixed time. If the CPU is operating normally, the CPU resets the WDT circuit before the WDT circuit times-up and restarts the timer operation. . However, the CPU went out of control and W
If the DT circuit cannot be reset before the time expires, the WDT circuit times out and C
A reset signal is output to the PU. Thereby, C
The PU is reset, and the runaway of the CPU is eliminated.

[0003]

However, such a W
In the method using the DT circuit, even if the CPU runs away, the WDT
Until the circuit times out, the CPU is not reset, and during that time, the CPU illegally accesses the memory, for example, and the stored contents of the memory are destroyed. Memory whose contents are destroyed is RAM or G / A
There is no problem as long as the memory is a volatile memory such as a register of (Gate-Array) and can be restored after resetting the CPU (that is, reset to a reset value or initialized by the CPU).
critical erasable program
Able ROM) and FLASH (flash) ROM
In the case of non-volatile memory such as, if the storage content of the memory that is not normally initialized is destroyed,
Even if the CPU is manually reset after the runaway, it is difficult to repair the destroyed stored contents.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to prevent the memory contents from being destroyed by quickly resetting the CPU when the CPU operates abnormally. An information processing device is provided.

[0005]

In order to achieve the above object, the present invention provides an information processing apparatus having a CPU and a memory accessed by the CPU. Area of the CPU
Access area determining means for determining whether or not the CPU is accessing based on an address signal output by the CPU, and the access area determining means determines that the CPU is accessing the unused area. And a CPU control means for outputting a reset signal to the CPU to reset the CPU. In the information processing apparatus according to the present invention, the access area determination unit includes a CPU
Unused areas in the memory space accessible by
It is determined whether or not U is accessing based on an address signal output by the CPU. When the access area determination means determines that the CPU is accessing the unused area, the CPU control means outputs a reset signal to the CPU to reset the CPU. That is,
When the CPU runs away and accesses an unused address area, the runaway of the CPU is detected thereby,
Is reset immediately. Therefore, when the CPU performs an abnormal operation, the CPU can be quickly reset and returned to the normal operation without waiting for the time-up in the timer operation as in the related art, thereby preventing the storage contents of the memory from being destroyed.

According to the present invention, there is provided an information processing apparatus including a CPU and a ROM accessed by the CPU.
When the CPU outputs an address signal for accessing the ROM and outputs a control signal indicating that writing to the memory is performed, the CPU outputs a reset signal to the CP.
U is provided with CPU control means for outputting to U and resetting the CPU. That is, in the information processing apparatus according to the present invention, when the CPU runs out of control and performs an illegal operation of writing data into the ROM, the CPU control means detects this and immediately resets the CPU. Therefore, when the CPU performs an abnormal operation, the CPU can be quickly reset and returned to the normal operation without waiting for the time-up in the timer operation as in the related art, thereby preventing the storage contents of the memory from being destroyed.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a main block diagram showing an example of an information processing apparatus according to the present invention, and FIG. 2 is a circuit diagram showing in detail a runaway write detection circuit block constituting the information processing apparatus of FIG. As shown in FIG. 1, a CPU 102 constituting an information processing apparatus 101 according to the present embodiment
Is connected to the EPROM (Elect) of 103 via the CPU bus 102A (for transmitting data, addresses, and control signals).
triprogrammableROM), 1
04 FLASH-ROM, 105 RAM, 106 EEPROM, and 107 G / A.

EPROM 103 and FLASH-RO
M104 holds program data (also simply called a program) necessary for the operation of the CPU 102. The RAM 105 and the EEPROM 106 are C
The PU 102 is used to hold data required for the operation. Volatile data, that is, data that does not need to be held when the power of the information processing apparatus 101 is turned off, needs to be held in the RAM 105 as nonvolatile data, that is, data that is held even when the power is turned off. Certain data is stored in the EEPROM 106.

The G / A 107 has an ADEC 108 inside.
(Address decoder circuit block), IPL109 (F
A program writing interface circuit block of the LASH-ROM 104), a WDT 110 (watchdog timer reset circuit block), and a WRDET 111
(Runaway write detection circuit block). The G / A 107 includes circuit blocks (not shown) for realizing various functions of the information processing apparatus 101, in addition to these components. FIG. 1 shows, in particular, only the components according to the invention.

The ADEC 108 generates chip select signals CS1 to CS7 of each external device, a write signal (write signal) WRB, and a read signal (read signal) RDB from signals supplied through the CPU bus 102A. The chip select signal CS1 is a signal which becomes “L” (low level) when the CPU 102 accesses the EPROM 103, and the chip select signal CS2 is F
LASH-ROM 104, chip select signal CS3 is RAM 105, chip select signal CS4 is EEPRO
M106, chip select signal CS5 is IPL109,
The chip select signal CS6 is a signal that becomes “L” when each of the WDTs 110 is accessed. Further, the chip select signal CS7 is set to ADEC10 in the G / A 107.
8, IPL109, WDT110, and WRDET
This signal is “L” when accessing a block (not shown) other than 111.

The IPL 109 is a FLASH-ROM 10
4 is controlled. FLASH-ROM104
A normal program is written in the FLASH-ROM 1 only when the program is updated.
04 is written. At this time, ADEC
108 outputs an “L” write signal WRB2 to the FLASH-ROM 104, and the IPL 109 outputs an “L” write enable signal I when the write is enabled.
Output PLB. That is, except when the program is updated, both the write enable signal IPLB and the write signal WRB2 become “H” (high level).

The WDT 110 is a circuit for detecting runaway of the CPU 102. The WDT 110 performs a timer operation for time-up in a fixed time. Usually, the CPU 102 resets the WDT 110 until the time-up, and restarts the timer operation. Start. That is, when the CPU 102 is operating normally, the WDT 110 does not time out. However, if the CPU 102 fails to reset the WDT 110 within a predetermined time due to runaway,
The DT circuit outputs an “L” reset signal RST1,
PU 102 is reset.

The WRDET 111 detects an erroneous write of the CPU 102. If an erroneous write is performed, the CPU determines that the CPU is in a runaway state and outputs an “L” reset signal RST2. Reset signal RST
1 and RST2 are transmitted to the CPU 10 through the AND circuit 112.
When an “L” reset signal is output from the WDT 110 or the WRDET 111 to the RST signal input terminal 2, the “L” reset signal is supplied to the CPU 102 and the CPU 102 is reset.

The WRDET 111 has a detailed configuration as shown in FIG. Reference numerals 202 to 210 in FIG. 2 denote logic circuits constituting the WRDET 111, respectively. When the CPU 102 accesses the FLASH-ROM 104, the chip select signal CS2 becomes "L". If the access at this time is a write, the write signal WRB becomes "L",
2 writes to the FLASH-ROM 104, the output of the OR circuit 203 is “L”;
H ”.

At this time, if the CPU 102 is updating the program, the write enable signal IPLB
Becomes “L”, and the write enable signal IPLB is input to the OR circuit 204 through the inverting circuit 202.
The output of the circuit 204 becomes “H”, and the output RST2 of the AND circuit 209 becomes “H”. When the program is not being updated, the write permission signal IPLB becomes “H”, and at this time, the CPU 102
4, the output of the OR circuit 203 becomes “L”.
And the output of the OR circuit 204 becomes “L”, and AN
The reset signal RST2 output from the D circuit 209 is “L”
Becomes

Similarly, the CPU 102
, The chip select signal CS1 changes to “
Since the CPU 102 only reads data from the EPROM 103 but does not perform writing, the write signal WRB is normally "H" when the chip select signal CS1 is "L" and the OR circuit 205 The output is "
H ”and the output RST2 of the AND circuit 209 becomes“ H ”.
Becomes

However, if the CPU 102 attempts to write to the EPROM 103, the chip select signal CS1
Is at "L" and the write signal WRB is at "L". In this case, the output of the OR circuit 205 is at "L".
The output RST2 of the D circuit 209 becomes "L".

Further, the chip select signals CS1 to CS
Since S7 is a chip select signal for each device allocated to the memory space of the CPU 102, AND
The output of the inversion circuit 207 connected to the output of the circuit 206 is stored in an unused area in the CPU memory space.
Becomes "L" when trying to access. Also, AN
Since the D circuit 210 becomes “L” when the CPU 102 performs a write or read operation, the OR circuit 20
8 becomes “L” when the CPU 102 performs a write or read operation on an unused area in the memory space,
At this time, the output signal of the AND circuit 209, that is, the reset signal RST2 becomes "L".

Next, the information processing apparatus 1 thus configured
01 will be described. A feature of the present invention lies in the operation of the WRDET 111 shown in FIG. That is, the WRDET 111 detects an operation that cannot be performed when the CPU 102 is performing a normal operation.
02 is reset. When the CPU 102 is performing a normal operation, the CPU 102
Writing to M106 is impossible. However, when the CPU 102 performs such an abnormal write operation by, for example, running out of control, the write signal WRB in FIG.
L ", and the chip select signal CS1 becomes" L. "At this time, the output of the OR circuit 205 (the reset signal generation circuit according to the present invention) becomes" L "(always in normal operation).
H "), an abnormal operation of the CPU 102 is detected. When the abnormal operation is detected, the reset signal RST2 output from the AND circuit 209 becomes" L ".
When the signal becomes "L", the reset signal RST output from the AND circuit 112 in FIG. 1 becomes "L", the CPU 102 is reset, and the CPU 102 stops the abnormal operation.

Next, the CPU 102 operates as a flash-ROM.
The operation in the case where data is written to the memory 104 will be described. The IPL 109 (the ROM according to the present invention) shown in FIG.
The control circuit outputs the write enable signal IPLB of “L” during the program update of the FLASH-ROM 104, but during normal operation, the write enable signal I of “H” is output.
Output PLB. When writing to the FLASH-ROM is not originally performed, the CPU 102 sets the FLASH-R
When a write operation is performed on the OM 104, the write enable signal IPLB is “H”, the write signal WRB is “L”, and the chip select signal CS2 is “L” in FIG.
Becomes At this time, the output of the OR circuit 203 becomes “L”, the output of the OR circuit 204 also becomes “L”, and the reset signal RST2 output from the AND circuit 209 becomes “L”. When the reset signal RST2 becomes "L", A in FIG.
The reset signal RST output from the ND circuit 112 is “L”
And the CPU 102 is reset, and the CPU 10
2 stops the abnormal operation. Here, the OR circuit 203, the inverting circuit 202, and the OR circuit 204 function as a reset signal generating circuit according to the present invention.

Further, when the CPU 102 accesses any of the memories allocated in the memory space of the CPU 102, one of the chip select signals CS1 to CS7 in FIG. 2 always becomes "L". At this time, the output of the AND circuit 206 in FIG. 2 is “L”, the output of the OR circuit 208 is “H”, and the reset signal RST2 output from the AND circuit 209 is “H”.

On the other hand, when the CPU 102 does not access the memory allocated to the memory space, all the chip select signals CS1 to CS7 become "H". At this time, the output of the AND circuit 206 in FIG. "H"
become. When the CPU 102 is operating normally,
When the output of the AND circuit 206 in FIG. 2 is “H”, the write signal WRB is “L” or the read signal RDB is “H”.
L ”, but when the CPU 102 performs an abnormal operation and performs a write operation or a read operation on an unused area not allocated to the memory space, the AN of FIG.
The output of the D circuit 206 is “H”, the output of the inversion circuit 207 is “L”, and the output of the AND circuit 210 is “L” because the write signal WRB or the read RDB is “L”.
Becomes At this time, the output of the OR circuit 208 in FIG.
L, and the reset signal RST2 output from the AND circuit 209 becomes "L." As a result, the reset signal RST output from the AND circuit 112 in FIG.
A reset is applied to the CPU 102, and the CPU 102 stops the abnormal operation. Here, the AND circuit 206 and the inversion circuit 207 are the first logic circuit according to the present invention, the AND circuit 2
10 functions as a second logic circuit according to the present invention,
The OR circuit 208 functions as a reset signal generation circuit according to the present invention.

The present embodiment is merely an example, and the configuration of the memory is not limited to this example. For example, without including EPROM 103, FLASH
The present invention is of course also effective in the case of only the ROM 104 or the case of not including the EEPROM 106. Also,
Write permission signal IPLB in IPL 109 of FIG.
, A signal indicating a write permission state is also generated for the EEPROM 106, and when the EEPROM 106 is not in the write permission state, the CPU 102
It is also possible to adopt a configuration in which a reset is applied to the CPU 102 when writing is to be performed.

[0024]

As described above, the present invention provides a CPU
An address signal output by the CPU as to whether or not the CPU is accessing an unused area in a memory space accessible by the CPU. Access area determining means for determining based on the access area determining means, and when the access area determining means determines that the CPU is accessing the unused area, the CPU outputs a reset signal to the CPU.
And a CPU control means for outputting to the CPU and resetting the CPU. In the information processing apparatus according to the present invention, the access area determination means determines whether or not the CPU is accessing an unused area in the memory space accessible by the CPU based on an address signal output from the CPU. When the access area determination means determines that the CPU is accessing the unused area, the CPU control means outputs a reset signal to the CPU to reset the CPU. That is, when the CPU goes out of control and accesses an unused address area, the runaway of the CPU is detected thereby, and the CPU is immediately reset. Therefore, when the CPU performs an abnormal operation, the CPU can be quickly reset and returned to the normal operation without waiting for the time-up in the timer operation as in the related art, thereby preventing the storage contents of the memory from being destroyed.

According to the present invention, there is provided an information processing apparatus comprising a CPU and a ROM accessed by the CPU.
When the CPU outputs an address signal for accessing the ROM and outputs a control signal indicating that writing to the memory is performed, the CPU outputs a reset signal to the CP.
U is provided with CPU control means for outputting to U and resetting the CPU. That is, in the information processing apparatus according to the present invention, when the CPU runs out of control and performs an illegal operation of writing data into the ROM, the CPU control means detects this and immediately resets the CPU. Therefore, when the CPU performs an abnormal operation, the CPU can be quickly reset and returned to the normal operation without waiting for the time-up in the timer operation as in the related art, thereby preventing the storage contents of the memory from being destroyed.

[Brief description of the drawings]

FIG. 1 is a main block diagram showing an example of an information processing apparatus according to the present invention.

FIG. 2 is a circuit diagram showing in detail a runaway write detection circuit block constituting the information processing apparatus of FIG. 1;

[Explanation of symbols]

101 ... information processing device, 102 ... CPU, 103 ...
… EPROM, 104… FLASH-ROM, 105
…… RAM, 106 …… EEPROM, 107 …… G /
A, 108 ADEC (address decoder circuit block), 109 IPL (program write interface circuit block), 110 WDT (watchdog timer reset circuit block), 111 WR
DET (runaway write detection circuit block), 112, 2
06, 209, 210 ... AND circuit, 203, 20
5, 204, 208 ... OR circuit, 202, 207 ...
Inverting circuit.

Claims (7)

[Claims] 1. An information processing apparatus comprising a CPU and a memory accessed by the CPU, wherein the CPU determines whether an unused area in a memory space accessible by the CPU is accessed by the CPU. C
An access area judging means for judging based on an address signal output by the PU; and the access area judging means outputs a reset signal to the CPU when the CPU judges that the unused area is being accessed. C to reset the CPU
An information processing apparatus comprising: a PU control unit. 2. The memory comprises a plurality of memory circuits, and outputs a chip select signal to the memory circuit based on an address signal output by the CPU, and a write signal or a read signal based on a control signal output by the CPU. The access area determining means receives the chip select signal output from the address decoder circuit as an input, and the address record circuit does not output any of the chip select signals. A first logic circuit that outputs a logic signal of a specific logic level; a write signal and a read signal output by the address decoder circuit; and a specific logic level when the address decoder circuit outputs the write signal or the read signal. Logical signal A second logic circuit that outputs the reset signal to the CPU when the first and second logic circuits both output the logic signal of the specific logic level. The information processing apparatus according to claim 1, further comprising a generation circuit. 3. The memory circuit according to claim 2, wherein the memory circuit is a RAM, an EPRO.
3. The information processing apparatus according to claim 2, wherein the information processing apparatus is one or more of an M, an EEPROM, a gate array, and a flash ROM. 4. A CPU and an R accessed by the CPU.
An information processing device including the OM, when the CPU outputs an address signal for accessing the ROM and outputs a control signal indicating that writing to a memory is performed, resets the reset signal to the CP.
An information processing apparatus comprising: CPU control means for outputting to U and resetting the CPU. 5. An address decoder circuit that outputs a chip select signal to the ROM based on an address signal output by the CPU and outputs a write signal to a memory based on the control signal output by the CPU. CPU control means receives the chip select signal and the write signal output from the address decoder circuit as inputs, and outputs the reset signal when the address decoder circuit outputs the chip select signal and the write signal simultaneously. The information processing apparatus according to claim 4, further comprising a reset signal generation circuit. 6. The information processing apparatus according to claim 5, wherein said ROM is an EPROM. 7. The ROM is a flash ROM or an E-ROM.
An EPROM for outputting a write enable signal when writing data to the flash ROM or the EEPROM;
An OM control circuit, wherein the reset signal generation circuit resets when the address decoder circuit simultaneously outputs the chip select signal and the write signal while the ROM control circuit is not outputting a write enable signal. The information processing device according to claim 5, wherein the information processing device outputs a signal.