JPS6074059A - Access control system for storage device - Google Patents

Abstract

PURPOSE:To decide whether accessing is allowed or not at a high speed by setting the address range of a storage device which is capable or incapable of accessing for every program different in execution level which is executed in time-division basis. CONSTITUTION:An address register 1 holds an address for accessing a control storage, and a program execution level deciding circuit 3 inputs an execution request signal 7 to determine the execution level of a program to be executed, and also transfers the result to an execution level register 4. Starting-point and ending-point registers 5 and 6 which determine the lower limit and upper limit of accessible addresses are selected according to the contents of the execution level register 4. A comparing circuit 2 compares the value Z of the address register 1 with the selected values of the starting-point and ending-point registers 5 and 6, i.e. Y and X, thereby outputting an access inhibition signal 8 when Z>Y or when Z<X.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a data processing device, and particularly to a data processing device capable of time-sharing execution of multiple programs with different execution levels. The present invention relates to a storage device access control method that can quickly detect and prevent erroneous storage device accesses by different programs.

[Conventional technology and problems]

FIG. 1 is a diagram showing one configuration example of a data processing system. In FIG. 1, 01 is a control memory, 02 is a microcode processing device, 03 is a main memory, 04 is a central processing unit, and 05 and 06 are channel devices.

BACKGROUND ART Conventionally, central processing units of computer systems capable of multiprocessing have adopted a memory protection mechanism for the main memory for the purpose of detecting access exceptions to the main memory by a program. One of the commonly known methods is
In addition to having a program hold a specific access key, a means for holding a similar access key and the type of access protected by the access key for each fixed address range of the main memory is provided. At the time of access, it is determined whether or not access is possible by comparing access keys. According to this method, a useful means with excellent versatility can be obtained. However, in the case of a data processing device designed for a specific purpose, that is, a device that does not pursue general versatility and requires high-speed access to a storage device, the above-mentioned method is not suitable for circuit response. It has various drawbacks in terms of performance, complexity, and cost.

One example of the application of such a device is a microcode processing device in the case where a data processing system as shown in FIG. 1 is configured using microcode. In this case, microcode is used to realize various functional parts such as the central processing unit 04, channel devices 05 and 06, and input/output control device (not shown) to configure the data processing system shown in FIG. Same microcode processing device 02
It is often used to configure the system to be executed in a time-sharing manner. Microcode is microcode processing device 0
The access operation of the control memory 01 requires much faster operation characteristics than the access of the main memory 03 by the central processing unit 04.

Furthermore, microcodes in charge of the various functional parts generally use the control memory 01 as a temporary storage area for control data, for example, the channel device 05 uses it as a subchannel storage area.

In this case, it is absolutely necessary to avoid destroying an unintended part of the control memory 01, for example, an area where the microcode is stored, due to an erroneous data storage operation of the microcode of a certain functional part. because,
This is because losing the microcode in the control memory 01 is equivalent to a fixed failure in the central part of the hardware, and will fatally impair the functionality of the entire data processing system. In such cases, it can be said that having effective checking means for accessing the control memory 01 is of extremely important concern.

[Purpose of the invention]

The present invention is based on the above consideration, and has a function that allows setting the address range of a storage device that is accessible or inaccessible at each execution level for each of multiple programs executed at different execution levels in a time-sharing manner. It is an object of the present invention to provide a storage device access control method that can quickly determine whether or not an access operation is possible based on an address value when accessing a storage device.

[Structure of the invention]

To this end, the storage device access control method of the present invention provides a data processing system that includes a storage device for storing instructions and/or data, and a data processing device that can execute multiple programs with different execution levels in a time-sharing manner. In the above, an access range control register consisting of a start point address register and an end point address register for holding the address range of the storage device that can be accessed or cannot be accessed by the program at each execution level is provided. The access range is provided for each program execution level of the data processing device, and the access range corresponds to the execution level of the program being processed when the data processing device accesses the storage device. A comparison circuit is provided to check whether or not the access range is within the access range of a control register, and the storage device access operation is prohibited or permitted based on the output of the comparison circuit, and further includes:
A flag register indicating the type of storage device access to be controlled to prohibit or permit storage device access operations is added to the access control range register, and a flag register is added to the access control range register, and a flag register is added to the access control range register, and a flag register is added to the access control range register to indicate the type of storage device access to be controlled to prohibit or permit storage device access operations. This feature is characterized in that it is possible to prohibit access or control permission only for those users.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing the configuration of one embodiment of the present invention, and FIG. 3 is a diagram showing the configuration of another embodiment of the present invention in which a flag register is added. In the figure, 1 is an address register, 2 is an address comparison circuit, 3 is a program execution level determination circuit, 4 is an execution level register, 5 is a start point register, 6 is an end point register, 7 is an execution request signal, and 8 is an access prohibition 9 is a flag register, and 10 to 12 are AND circuits.

The present invention will be described in detail below as a part of a general microcode processing device, but portions of the microcode processing device that are not directly related to the present invention are not illustrated.

Here, it is assumed that the microcode processing device has four program execution levels called A%BhC and D, and processes programs at each level in a time-sharing manner according to execution requests.

In FIG. 1, an address register 1 holds an address for accessing the control memory, and a program execution level determining circuit 3 includes priority comparison logic and receives an execution request signal 7 for processing. In addition to determining the execution level of the program to be executed, the results are
Transfer to register 4. The starting point register 5 holds the lower limit of accessible addresses, and the ending point register 6 holds the upper limit of accessible addresses, and these constitute an access range control register. And (α) to d, ) correspond to the program execution level person to D, respectively.

Here, the contents of the execution level register 4 are used to select the access range control register corresponding to the determined program execution level. Comparison circuit 2 compares value 2 of address register 1 with value Y of selected start point register 5 and value X of end point register 6, and determines whether z>Y or z
When <X, access prohibition signal 8 is output. That is,
The access prohibition signal 8 indicates that the address of the control memory to be accessed is beyond the address range that can be accessed by the program being executed. This access prohibition signal 8 is transmitted by a circuit not shown as one of the conditions for inhibiting write pulse signals to the control memory (write mining control) or as one of the conditions for inhibiting read data from the control memory (read mining control). used.

FIG. 3 shows another embodiment of the present invention.

In FIG. 3, the structure and operation of a portion 100 surrounded by broken lines are exactly the same as in the embodiment shown in FIG.

In this embodiment, a flag register 9 is added to each of the access range control registers, and similarly (α) to d,) correspond to program execution levels MAN to D.

The flag register 9 is made up of 3 bits and specifies the three types of accessible types, ``instruction read'', ``data read'', and ``data write'', corresponding to the bits.
It is used to condition the access inhibit signal in AND circuits 10-12. Therefore, by using the output signals 13 to 15, it becomes possible to individually control instruction read prohibition, data read prohibition, and data write prohibition, respectively.

In the above embodiment, the access range control register is used to specify an accessible address range, but conversely, even if the configuration is configured to specify an inaccessible address range, the effect is exactly the same. be. Furthermore, as in the embodiment shown in FIG. 3, by expanding the flag register, one of the above-mentioned designation methods may be selected for each access range control register.

In addition, the specific program execution level of the processing device is
It is also easily possible to exclude it from access prohibition control. Furthermore, a means for disabling or enabling the access prohibition control may be provided by specifying a program or by some external means. Further, the access range control register may be a fixed pattern generation means such as a switch or ROM, or may be a variable value setting means accessible from a program or some external device. As is clear from the above, according to the present invention, a storage device access control mechanism capable of high-speed response can be added with a relatively simple circuit configuration. This has the effect of improving the reliability and data integrity of the entire data processing system.

[Brief explanation of the drawing]

Figure 1 is a diagram showing an example of the configuration of a data processing system;
The figure shows the configuration of one embodiment of the present invention, and FIG.
It is a figure which shows the structure of another Example of this invention which added the register. 01... Control memory, 02... Microcode processing device, 03... Main storage device, 04... Central processing unit,
05 and 06...Channel device, 1...Address register, 2...Address comparison circuit, 3...Program execution level determination circuit, 4...Execution level register, 5...Start point register , 6... End point register, 7.
...Execution request signal, 8...Access prohibition signal, 9...
- Flag register, 10 to 12...AND circuit. Patent Applicant: Fujitsu Limited Representative Patent Attorney Yotsube Kyotani

Claims (2)

[Claims] (1) In a data processing system equipped with a storage device for storing instructions and/or data, and a data processing device capable of time-sharing execution of multiple programs at different execution levels, the programs at each execution level are An access range control register consisting of a start point address register and an end point address register for holding the address range of the storage device that can be accessed or cannot be accessed by the data processing device is provided for each program execution level of the data processing device. and whether the value of the access address is within the access range of the access range control register corresponding to the execution level of the program being processed when the data processing device accesses the storage device. 1. A storage device access control method, characterized in that a comparison circuit is provided to check whether the storage device access operation is prohibited or not, and the prohibition or permission of the storage device access operation is controlled based on the output of the comparison circuit. (2) In a data processing system equipped with a storage device for storing instructions and/or data, and a data processing device that executes multiple programs at different execution levels in a time-sharing manner, the programs at each execution level A start point address register and an end point address register for holding the address range of the storage device that can be accessed or cannot be accessed by the user, and storage device access that is subject to control for prohibiting or permitting storage device access operations. An access range control register consisting of a flag register indicating the type of storage device is provided for each program execution level of the data processing device, and when the data processing device accesses the storage device, the access range control register is A comparison circuit is provided to check whether the value of is within the access range of the access range control register corresponding to the execution level of the program being processed, and the output of the comparison circuit is determined by the value specified by the flag register. 1. A storage device access control method, characterized in that access can be prohibited or permitted only for specific types of storage device access.