JPS6073762A - Memory protective system - Google Patents

Memory protective system

Info

Publication number
JPS6073762A
JPS6073762A JP58181164A JP18116483A JPS6073762A JP S6073762 A JPS6073762 A JP S6073762A JP 58181164 A JP58181164 A JP 58181164A JP 18116483 A JP18116483 A JP 18116483A JP S6073762 A JPS6073762 A JP S6073762A
Authority
JP
Japan
Prior art keywords
bit
circuit
address
program
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58181164A
Inventor
Seiichi Sugaya
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58181164A priority Critical patent/JPS6073762A/en
Publication of JPS6073762A publication Critical patent/JPS6073762A/en
Application status is Pending legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14Protection against unauthorised use of memory or access to memory

Abstract

PURPOSE:To improve the reliability of a data processing system and data maintenability by setting an accessible memory unit area to every plural programs, and by discriminating whether or not access is possible according to the address at the time of access to the memory device. CONSTITUTION:An address registor 1 stores the address at the time of control memory access, and is composed of 14 ibts. A high-order bit part 1a is composed of four bits. A decoding circuit 2 decodes high-order four bits and outputs one signal out of block discrimination signals 10. A program execution level determination circuit 3 includes priority comparing logic, and inputs an execution demand signal 8 to determine an execution level of a program to be processed. Said circuit 3 transfers its result to a program level registor 4. Out of memroy protective registors 5, 5a-5d correspond to program execution levels A-D, respectively, and each bit is a write permission flag. And circuits 6-0-15 and an OR circuit 7 execute operation bit by bit between each bit and the block discrimination signals 10, and generate a write permission signal 9.
JP58181164A 1983-09-29 1983-09-29 Memory protective system Pending JPS6073762A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58181164A JPS6073762A (en) 1983-09-29 1983-09-29 Memory protective system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58181164A JPS6073762A (en) 1983-09-29 1983-09-29 Memory protective system

Publications (1)

Publication Number Publication Date
JPS6073762A true JPS6073762A (en) 1985-04-25

Family

ID=16096001

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58181164A Pending JPS6073762A (en) 1983-09-29 1983-09-29 Memory protective system

Country Status (1)

Country Link
JP (1) JPS6073762A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6252637A (en) * 1985-08-30 1987-03-07 Advanced Micro Devices Inc Digital processor control
JPH02222035A (en) * 1989-02-23 1990-09-04 Nec Corp Microprogram controller
JP2004537786A (en) * 2001-06-08 2004-12-16 ヒューレット・パッカード・カンパニーHewlett−Packard Company Secure machine platform to interface with the operating system and customized control program

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6252637A (en) * 1985-08-30 1987-03-07 Advanced Micro Devices Inc Digital processor control
JPH02222035A (en) * 1989-02-23 1990-09-04 Nec Corp Microprogram controller
JP2004537786A (en) * 2001-06-08 2004-12-16 ヒューレット・パッカード・カンパニーHewlett−Packard Company Secure machine platform to interface with the operating system and customized control program

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