KR920002829B1 - Memory access control system - Google Patents

Abstract

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Description

Memory access control system

1 is a block diagram of a computer system in accordance with the present invention.

FIG. 2 is a detailed block diagram of the address decode controller of FIG.

3 and 5 are flowcharts illustrating operations for an embodiment of the present invention.

4 and 6 illustrate memory maps illustrating operations for embodiments of the present invention.

* Explanation of symbols for main parts of the drawings

11 CPU (Central Processing Unit) 12 RAM

13: ROM 14: Address Decode Controller

15: other input / output device 141: address decode control register

161: address signal 162: control signal

The present invention relates to a memory access control system, and more particularly, to a memory access control system for a high performance computer system.

In recent years, with advances in semiconductor technology, values of microprocessors, memory devices, peripheral control LSIs, and the like have become inexpensive. Thus, a high performance computer system can be assembled with the appropriate combination of these components.

An example of a high-performance computer system is a personal computer. According to such a personal computer system, BIOS, which stands for Basic Input / Output System, is written to ROM rather than RAM because RAM is in an indeterminate state when the power is turned on. to be. Therefore, in order to run the BIOS, the CPU must first access the ROM.

For lap-top personal computers, some large RAMs are preferred over many small RAMs in terms of space savings. In such a case, each large RAM may have an unused area.

The access time of ROMs typically requires more than twice the access time of RAMs. Thus, when the same program is stored in ROM and RAM having the same data bus width, the access time for the ROM takes longer than the access time for the RAM.

In a personal computer system having a data processing capacity of 32 bits, for example, for cost reduction, a personal computer system is configured by using a RAM accessed by a 32 bit data bus and a ROM accessed by a 16 bit data bus. Programs stored in RAM in these systems can be accessed at once using the 32-bit data bus. On the other hand, a program stored in a ROM must be accessed twice (using half of the data at a time) with the use of a 16-bit data bus, so for cost savings, a ROM associated with a 16-bit data bus can run a 32-bit program in a ROM. Program processing is slower than using the data bus.

The problem with the high performance computer system described above is that the execution time of the BIOS stored in the ROM takes longer than the execution time of the BIOS stored in the RAM.

It is therefore an object of the present invention to provide a memory access control system that can reduce the information stored in a ROM, such as the time required to execute a BIOS. In order to achieve this object of the present invention, a memory access control system for a computer system of the present invention includes a RAM and ROM coupled to each other by a system bus, a CPU for performing data processing, and contents of a ROM when initializing the system. Means for copying at least a portion of the data to the RAM, and means for making the address of the RAM the same as the address of the ROM so that the contents of the ROM copied to the RAM can be obtained from the RAM.

m의 조건을 만족시켜야함에 유의해야 한다.Referring now to FIG. 1, the personal computer system of the present invention includes a CPU 11, a RAM 12, and a ROM 13. The CPU 11, which is an essential part of the system, controls the operation of the system according to the program stored in the RAM 12 and the ROM 13 and the input / output device coupled to the system by n-bit data processing. An OS (operating system) and an application program are stored in RAM 12 associated with the bus width of n-bit data. The RAM 12 also has an area for storing the BIOS copied from the ROM 13. The area for storing the BIOS is allocated, for example, to an unused area of RAM having a large capacity of 1M bits. The bus width of the m-bit data is associated with ROM 13, which stores the BIOS and data depending on the system. So bus width m and n is n

Note that the condition of m must be satisfied.

The address decode controller 14 copies the BIOS from the ROM 13 area to the RAM 12 area having the same address as the ROM area so that the contents of the ROM 13 can be obtained from the RAM 12. It has a function.

The purpose of storing the BIOS in the RAM 12 area having the same address as the area of the ROM 13 in which the BIOS is stored is to smoothly execute the BIOS without changing the contents of the BIOS.

As shown in FIG. 2A, the address decode controller 14 mainly consists of an address decode control register 141 and an address decode circuit 142. As shown in FIG. In response to a control signal input from the CPU 11 via the control bus 162, the address decode control register 141 is copied to the information address in the ROM 13 as the copy source and in the RAM 12 as the copy destination. The memory addresses are set so that the addresses of the information are equal to each other.

The address decode circuit 142 has comparators 210 and 220, as shown in FIG. 2B, and the first comparator 210 places the first input data A and RAM on top of an address sent through the bus 16. If the difference of the addresses to the second area 52 of (12) is set as the second input data B, and the first input data A and the second input data B coincide with each other, the RAM ( A signal C for allowing access to 12 is output.

The AND gate 230 which prohibits the output of the permission signal C when the write prohibition information D is set in the control register 141 and the write request signal E has been sent via the bus 16 as a control signal. The write protection is achieved by installing a. When the write prohibition information D is not set in the control register 141 or when the write request E is not sent even though it is set, the permission signal C is set by the AND gate 230 to the RAM ( 12) to allow access.

The reason for matching the address of the area storing the above-mentioned BIOS with the ROM and the RAM is that the object of the present invention is to copy the BIOS stored in the ROM into the RAM and read the BIOS from the RAM to improve the processing speed. Because there is.

Also, in order to maintain software compatibility, the BIOS must be stored in a fixed area. If the BIOS is stored in an area of an address different from the predetermined area, an operation of converting an address must be performed every time the BIOS is read out, the processing temperature is lowered, and the system configuration is complicated. By performing the operation of making the address of the BIOS stored in the RAM the same as the address of the ROM which was originally determined, the CPU accesses the predetermined address so that the BIOS can be read from the RAM. The access decode control register 141 also outputs a control signal to the address decode circuit 142 via the control bus 162. The address decode circuit 142 receives an address signal from the CPU 11 via the address bus 161 so as to decode an address signal in response to a control signal from the address decode control register 141, and also copies the copied BIOS into RAM ( 12, the address decoder circuit 142 outputs a selection signal 143 for selecting one of the RAM 12 and the ROM 13, and transmits the signal to the RAM 12 and the ROM 13; . The remaining components 15 of the system include input and output devices for entry, display and printing. The CPU 11, RAM 12, ROM 13, address decode controller 14 and input / output device 15 are interconnected by a system bus 16 consisting of an address bus, a data bus and a control bus.

3 and 5 are flowcharts and FIGS. 4 and 6 show memory maps for illustrating the operation of the memory access control system of the present invention. The operation of the personal computer system will be described below.

In order to operate the personal computer system, after the system is initialized, the CPU 11 executes a copy program stored in the ROM 13 to copy the BIOS from the ROM 13 to the RAM 12. At this time, the RAM address and the ROM address are equal to each other by use of the address decode controller 14. After copying the BIOS, the CPU 11 prevents other information from being written to the RAM 12 set to have the same address as the ROM 13. The CPU 11 also generates a ROM / RAM select signal 143 to cause the address decode circuit 142 to separate the ROM 13 and to execute the BIOS using the RAM 12 to execute the address decode control register. 141 is set. Thus, the BIOS can be executed at high speed.

Next, a method of copying the BIOS from the ROM 13 to the RAM 12 will be described in detail.

Figure 3 illustrates a flowchart of how to copy the BIOS. 4 shows a corresponding memory map. In FIG. 4, a) shows the memory map at the start of the system. The first RAM area 50 represents an area for storing application programs, the second RAM area 52 represents an area for copying the BIOS, and the ROM area 51 represents an area for storing the BIOS. The spare area of the first RAM area 50 is used as the second RAM area 52. By using this spare area, the storage area of the RAM 12 can be used more effectively. In step 20 of FIG. 3, the CPU 11 copies the BIOS stored in the ROM 13 to the RAM 12 under the condition of the memory map a. At the time of copying shown in FIG. 4B, the CPU 11 reads data from the ROM area 51 and writes the read data into the second RAM area 52. After copying, the address decode control register 141 is set so that the ROM area 51 is separated from the CPU 11 by the ROM / RAM selection signal 143, and the second RAM area 52 is removed in step 21. Write protection is prevented. As shown in FIG. 4C, in the memory map after the copying process, the ROM area 51 is separated from the CPU 11 and shifted to a non-access area that cannot be accessed by the CPU 11. At this time, the second RAM area 52 is maintained in the write protection state.

Next, a copying method different from the above is described in Figs. 5 and 6, where Fig. 5 is a flowchart illustrating the copying method, and Fig. 6 shows a memory map. 6A is a memory map at system startup. In the memory map, as shown in FIG. 3, the first RAM area 53 is an application program area, the second RAM area 55 is an area for copying the BIOS, and the ROM area 54 is an area in which the BIOS is stored. The second RAM area 55 is initially separated from the CPU 11 and is located in a back area that is not accessible by the CPU 11. In step 22 of FIG. 5, first, the address decode control register 141 is set to be in the state shown in FIG. 6B. That is, the CPU 11 reads data from the ROM 13 and writes the data into the RAM 12. In this state, since the CPU 11 executes the BIOS copy program stored in the ROM 13, reading data from the ROM area 54 and writing data into the second RAM area 55 prevent copying of the BIOS. It is done repeatedly (FIG. 5, step 23). After the BIOS is copied, the address decode control register 141 is set. The ROM area 54 is separated from the CPU 11 by the ROM / RAM select signal 143, and the second RAM area 55 is write-protected in step 23 of FIG. As shown in FIG. 6C, the ROM area 54 is shifted to the back area for separation from the CPU 11, and the second RAM area 55 is kept in the write protection state.

In the above manner, the BIOS is copied to the RAM 12 so that the RAM routines can be executed at high speed.

Claims (5)

A memory access control system for a data processing apparatus in which data is processed in accordance with at least a partial initial arrangement state of a device that is automatically set during operation, the memory access control system comprising: a RAM 12 and a plurality of addresses respectively corresponding to a predetermined data memory area; A system bus (16) for interconnecting the ROM (13) and the RAM (12) and the ROM (13); Data processing is performed using the data stored in the RAM 12 and the ROM 13, and the data stored in the ROM 13 in response to at least a portion of predetermined system data in the ROM 13 during the start-up operation of the apparatus. A CPU 11 including means for automatically copying at least a portion into the RAM 12; Means (141, 142) for copying the same data and assigning an address corresponding to the same memory area as the address corresponding to the memory area of the ROM 13 so that a portion of the copied data is quickly accessed into the RAM 12; And a memory access control system. 2. The RAM 12 according to claim 1, wherein the RAM 12 has a data bus width of n bits, the ROM 13 has a data bus width of m bits, and the CPU 11 has n bits of data under the condition n> m. And a memory access control system. 2. The RAM of claim 1, wherein the RAM 12 has an n-bit data bus width, the ROM 13 has an m-bit data bus width, and the CPU 11 has n-bit data with n = m conditions. And a memory access control system. The memory access control system according to claim 1, further comprising means (142) for preventing data of the ROM (13) copied into the RAM (12) from being accessed by the CPU (11). . 5. The memory access control system as claimed in claim 4, wherein said prevention means (142) comprises means for selecting at least a portion of a memory area of a RAM (12) for selecting an access inhibited signal by a CPU (11).

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